High-K materials and metal gates for CMOS applications

J Robertson, RM Wallace - Materials Science and Engineering: R: Reports, 2015 - Elsevier
The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the
silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current …

A review of NBTI mechanisms and models

S Mahapatra, N Parihar - Microelectronics Reliability, 2018 - Elsevier
A comprehensive review is done of different NBTI mechanisms and models proposed in the
literature over the past years. The Reaction-Diffusion (RD) model based comprehensive …

CMOS reliability from past to future: A survey of requirements, trends, and prediction methods

I Hill, P Chanawala, R Singh… - … on Device and …, 2021 - ieeexplore.ieee.org
Developments in IC fabrication, emerging high-reliability markets, and government
regulations indicate potential for significant shifts in how reliability fits within IC development …

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability

B Kaczer, J Franco, P Weckx, PJ Roussel… - Microelectronics …, 2018 - Elsevier
A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed
understanding of their properties. A model with trap energy levels in the gate dielectric and …

A 3-D TCAD framework for NBTI—Part I: Implementation details and FinFET channel material impact

R Tiwari, N Parihar, K Thakor, HY Wong… - … on Electron Devices, 2019 - ieeexplore.ieee.org
The time kinetics of interface trap generation and passivation (ΔN IT) and its contribution (ΔV
IT) during and after negative bias temperature instability (NBTI) stress is calculated by using …

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

Y Zhang, X Ai, X Yin, H Zhu, H Yang… - … on Electron Devices, 2021 - ieeexplore.ieee.org
We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS)
field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs …

Modeling of NBTI using BAT framework: DC-AC stress-recovery kinetics, material, and process dependence

S Mahapatra, N Parihar - IEEE Transactions on Device and …, 2020 - ieeexplore.ieee.org
Threshold voltage shift (ΔVT) due to Negative Bias Temperature Instability (NBTI) in p-
MOSFETs is modeled using the BTI Analysis Tool (BAT) framework. The ΔV T time kinetics …

Modeling of NBTI kinetics in RMG Si and SiGe FinFETs, part-I: DC stress and recovery

N Parihar, RG Southwick, M Wang… - … on Electron Devices, 2018 - ieeexplore.ieee.org
An ultrafast (10-μs delay) measurement technique is used to characterize the negative bias
temperature instability-induced threshold voltage shift (ΔV T) in replacement metal gate …

Toward understanding positive bias temperature instability in fully recessed-gate GaN MISFETs

TL Wu, J Franco, D Marcon, B De Jaeger… - … on Electron Devices, 2016 - ieeexplore.ieee.org
In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, ie, plasma-
enhanced atomic layer deposition (PEALD) SiN and ALD Al 2 O 3 gate dielectric, are used …

Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3

J Franco, A Alian, B Kaczer, D Lin… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53
Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel …