Digital circuit design challenges and opportunities in the era of nanoscale CMOS
Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
Improving GPU performance via large warps and two-level warp scheduling
V Narasiman, M Shebanow, CJ Lee… - Proceedings of the 44th …, 2011 - dl.acm.org
Due to their massive computational power, graphics processing units (GPUs) have become
a popular platform for executing general purpose parallel applications. GPU programming …
a popular platform for executing general purpose parallel applications. GPU programming …
Clock rate versus IPC: The end of the road for conventional microarchitectures
V Agarwal, MS Hrishikesh, SW Keckler… - Proceedings of the 27th …, 2000 - dl.acm.org
The doubling of microprocessor performance every three years has been the result of two
factors: more transistors per chip and superlinear scali ng of the processor clock with …
factors: more transistors per chip and superlinear scali ng of the processor clock with …
[PDF][PDF] Cacti 3.0: An integrated cache timing, power, and area model
P Shivakumar, NP Jouppi - 2001 - cs.utexas.edu
CACTI 3.0 is an integrated cache access time, cycle time, area, aspect ratio, and power
model. By integrating all these models together users can have confidence that tradeoffs …
model. By integrating all these models together users can have confidence that tradeoffs …
Scaling trends of digital single-event effects: A survey of SEU and SET parameters and comparison with transistor performance
D Kobayashi - IEEE Transactions on Nuclear Science, 2020 - ieeexplore.ieee.org
The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …
Multi-bit error tolerant caches using two-dimensional error coding
In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make
embedded memories increasingly vulnerable to reliability and yield problems. As scaling …
embedded memories increasingly vulnerable to reliability and yield problems. As scaling …
Dark memory and accelerator-rich system optimization in the dark silicon era
Unlike traditional dark silicon works that attack the computing logic, this article puts a focus
on the memory part, which dissipates most of the energy for memory-bound CPU …
on the memory part, which dissipates most of the energy for memory-bound CPU …
A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies
S Thoziyoor, JH Ahn, M Monchiero… - ACM SIGARCH …, 2008 - dl.acm.org
In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds
support for modeling of commodity DRAM technology and support for main memory DRAM …
support for modeling of commodity DRAM technology and support for main memory DRAM …