In this paper, we propose a methodology to model and optimize FinFET devices for robust
and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to …

Parameter variations pose an increasingly challenging threat to the CMOS technology
scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant …

With the continuous shrinking of transistors and advent of new transistor architectures to
keep in pace with Moore's law and ITRS goals, there is a rising interest in multigate 3D …

In this brief, electrical characteristics of 25-nm round-top-gate fin-typed field-effect transistors
(FinFETs) on silicon wafers are numerically explored. With an ideal fin angle (ie, thetas …

The variability due to the displacement damage defect is investigated for various bulk
FinFET technology nodes. A random displacement damage from point to clustered defects is …

As Fin Field Effect Transistor (FinFET) scales aggressively, even a single point defect
becomes a source of performance variability. The point defect is inevitably introduced not …

With emerging three-dimensional device architectures for advanced silicon devices such as
fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize …

Front-end processing mostly deals with technologies associated to junction formation in
semiconductor devices. Ion implantation and thermal anneal models are key to predict …

In this study, we derive an analytical model of an electric potential of a double-gated (DG)
fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's …

In this work, the effect of displacement defect (DD) owing to cosmic rays on six-transistor (6T)
static random access memory (SRAM) with a 3 nm node nanosheet field-effect transistor …