Monolithic three dimensional integration of semiconductor integrated circuits
Y Du - US Patent 9,177,890, 2015 - Google Patents
(57) ABSTRACT A three-dimensional integrated circuit comprising top tier nanowire
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
3D floorplanning using 2D and 3D blocks
The disclosed embodiments are directed to systems and method for floorplanning an
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
Y Du - US Patent 9,536,840, 2017 - Google Patents
(57) ABSTRACT A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related methods
Y Du, J Xie, K Samadi - US Patent 9,041,448, 2015 - Google Patents
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related
method are disclosed. In one embodiment, a single clock source is provided for the 3DIC …
method are disclosed. In one embodiment, a single clock source is provided for the 3DIC …
Clock distribution network for 3D integrated circuit
5,724,557 A* 3/1998 McBean, Sr.................. T16, 113 2011/O121366 A1 5/2011 Or-Bach et
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
[图书][B] Analysis and design of resilient VLSI circuits: mitigating soft errors and process variations
R Garg - 2009 - books.google.com
This monograph is motivated by the challenges faced in designing reliable VLSI systems in
modern VLSI processes. The reliable operation of integrated circuits (ICs) has become …
modern VLSI processes. The reliable operation of integrated circuits (ICs) has become …
A fully integrated Li-ion-compatible hybrid four-level DC–DC converter in 28-nm FDSOI
SS Amin, PP Mercier - IEEE journal of solid-state circuits, 2018 - ieeexplore.ieee.org
This paper presents a Li-ion-compatible fully integrated hybrid dc-dc converter implemented
in 28-nm FDSOI. A modified four-level converter is proposed to achieve high efficiency while …
in 28-nm FDSOI. A modified four-level converter is proposed to achieve high efficiency while …
Ultra low voltage level shifters to interface sub and super threshold reconfigurable logic cells
A Chavan, E MacDonald - 2008 IEEE Aerospace Conference, 2008 - ieeexplore.ieee.org
Ultra-low power consumption often comes at the price of reduced performance for energy
conscious electronics-particularly reconfigurable circuits. Operating devices at ultra-low …
conscious electronics-particularly reconfigurable circuits. Operating devices at ultra-low …
Architecture knowledge for evaluating scalable databases
Designing massively scalable, highly available big data systems is an immense challenge
for software architects. Big data applications require distributed systems design principles to …
for software architects. Big data applications require distributed systems design principles to …
Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
J Xie, Y Du - US Patent 9,171,608, 2015 - Google Patents
Abstract A three-dimensional (3D) memory cell separation among 3D integrated circuit
(IC)(3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also …
(IC)(3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also …