A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
AT Narayanan, M Katsuragi, K Kimura… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …
A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …
An adaptive pre-distortion technique to mitigate the DTC nonlinearity in digital PLLs
S Levantino, G Marzin, C Samori - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in
the design of frequency synthesizers for wireless applications. However, the main obstacle …
the design of frequency synthesizers for wireless applications. However, the main obstacle …
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH -TDC for Low In-Band Phase Noise
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …
A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method
A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking …
SM Dartizio, F Buccoleri, F Tesolin… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This work presents a fast-locking and low-jitter fractional-bang-bang phase-locked loop
(BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs …
(BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs …
Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers
An all-digital reconfigurable multi-output clock generator is presented. A digital phase-
locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional …
locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional …
Design methodology for phase-locked loops using binary (bang-bang) phase detectors
We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency
domain that is complete and self-consistent. It enables the manual design of frequency …
domain that is complete and self-consistent. It enables the manual design of frequency …
[HTML][HTML] Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art
This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …