The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will
be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links …

The choice of clock and data recovery (CDR) architecture in serial links dictates many of the
blocklevel circuit specifications (specs). Block-level specs ultimately determine the energy …

Recently, there has been a strong drive to replace established analog circuits for multi-
gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase …

In this brief, a half-rate (HR) bang-bang (BB) phase detector (PD) with multiple decision
levels is proposed for clock and data recovery (CDR) circuits. The combination allows the …

This article proposes a sub-sampled phase detector (PD) operating at a one-sixteenth rate
clock. Here, the objective is to achieve energy-efficient clock recovery in high-speed wireline …

Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in
communication systems for High-Energy Physics (HEP) since are used to generate a high …

In this paper, the design of subsampler and phase detector circuits at 14nm technology node
(FinFET) is presented. The design is carried out on cadence virtuoso with a supply voltage of …

In the recent communication system of electronic industry will focusing on high speed signal
processing application, with be assistance of optical to electrical data communications …

Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have
always been important block which have abundant applications such as digital signal …