Configurable router for a network on chip (NoC)
J Philip, S Kumar - US Patent 9,742,630, 2017 - Google Patents
Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …
such as a router, for implementation of a Network on Chip (NoC). The router is …
Systems and methods for facilitating low power on a network-on-chip
JA Bauman, J Rowlands, S Kumar - US Patent 10,452,124, 2019 - Google Patents
Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
Supporting multicast in NoC interconnect
Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …
multiple destination components from a source component. Multicast environment is …
System level simulation in Network on Chip architecture
S Kumar, A Patankar, E Norige - US Patent 10,496,770, 2019 - Google Patents
Abstract Systems and methods for performing multi-message transaction based
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
QoS in a system with end-to-end flow control and QoS aware buffer allocation
S Kumar - US Patent 9,769,077, 2017 - Google Patents
(Continued) Primary Examiner—Jay P Patel (74) Attorney, Agent, or Firm—Procopio, Cory,
Hargreaves & Savitch LLP (57) ABSTRACT The present disclosure is directed to Quality of …
Hargreaves & Savitch LLP (57) ABSTRACT The present disclosure is directed to Quality of …
Peripheral interconnect for configurable slave endpoint circuits
IA Swarbrick, DP Schultz - US Patent 10,621,129, 2020 - Google Patents
A peripheral interconnect for configuring slave endpoint circuits, such as may be in a
configurable network, in a system-on-chip (SOC) is described herein. In an example, an …
configurable network, in a system-on-chip (SOC) is described herein. In an example, an …
Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
J Philip, S Kumar - US Patent 9,825,809, 2017 - Google Patents
Aspects of the present disclosure relates to methods, computer readable mediums, and NoC
architectures/systems/constructions that can automatically mark and configure some …
architectures/systems/constructions that can automatically mark and configure some …
Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
E Norige, S Kumar - US Patent 9,185,023, 2015 - Google Patents
Systems and methods described herein are directed to solu tions for Network on Chip (NoC)
interconnects that automati cally and dynamically determines the position of hosts of various …
interconnects that automati cally and dynamically determines the position of hosts of various …
Generating physically aware network-on-chip design from a physical system-on-chip specification
R Chopra, YT Lin, S Kumar - US Patent 10,218,580, 2019 - Google Patents
Different example implementations of the present disclosure relates to methods and
computer readable mediums for automatically generating physically aware NoC design and …
computer readable mediums for automatically generating physically aware NoC design and …