The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …

Heavy-ion experimental results were used to characterize single-event upset trends in 16
nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data …

For advanced technology nodes, the close proximity of semiconductor regions results in
multiple regions collecting charge after an ion strike. This is especially true for static random …

Single-port (SP) and two-port (TP) static random access memory (SRAM) designs in a 5-nm
bulk FinFET node were tested for multicell upset (MCU) vulnerability against alpha particles …

For advanced technology nodes, the static random access memories (SRAMs) are highly
vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by …

In this work, single-event upset (SEU) responses of D flip-flop (FF) designs with different
threshold-voltage options in a 7-nm bulk FinFET technology are examined. Experimental …

This paper presents characterization results of soft error rate (SER) on logic circuits
manufactured with 14 nm High-k/metal gate bulk FinFET technology. The FinFET SER …

The angular sensitivity of neutron-induced single-event upsets (SEUs) is studied in 12-nm
FinFET SRAMs. Irradiation experiments are performed using a terrestrial environment …

This article investigates the single-event effects on 16-nm bulk field-effect transistors
(FinFETS) in terms of single-bit upsets and multiple-cell upsets under heavy ion irradiation …

Characterizing the sensitivity of a static random access memory (SRAM) to single-event
upset (SEU) is an essential task for assuring its soft-error reliability. However, this task often …