[HTML][HTML] A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays

W Wang, X Li, L Chen, H Sun, F Zhang - Sensors, 2024 - mdpi.com
Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space
applications are highly susceptible to single event effects, leading to soft errors in FPGAs …

Validation techniques for fault emulation of SRAM-based FPGAs

H Quinn, M Wirthlin - IEEE Transactions on Nuclear Science, 2015 - ieeexplore.ieee.org
A variety of fault emulation systems have been created to study the effect of single-event
effects (SEEs) in static random access memory (SRAM) based field-programmable gate …

Delay monitor circuit and delay change measurement due to SEU in SRAM-based FPGA

M Darvishi, Y Audet, Y Blaquière - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper presents a monitor circuit designed for the detection of extra combinational
delays in a high-frequency SRAM-based field-programmable gate array (FPGA). Since in …

[HTML][HTML] FPGA 在辐照环境下的故障注入系统研究

薛晓良, 苏海冰, 舒怀亮, 郭帅, 吴威 - 光电工程, 2019 - cn.oejournal.org
对Xilinx SRAM 型FPGA 的配置RAM 的帧物理组织进行了研究, 给出了提取帧结构的方法,
并给出了比特流中帧的排列顺序; 分析了SEM IP 核的中间文件的结构并给出了提取必要位的 …

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A Souari, C Thibeault, Y Blaquière, R Velazco - Microelectronics Reliability, 2016 - Elsevier
A novel fault injection approach, reproducing results obtained from radiation ground testing
while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable …

Improving FPGA resilience through Partial Dynamic Reconfiguration

JL Nunes - arXiv preprint arXiv:1608.06559, 2016 - arxiv.org
This paper explores advances in reconfiguration properties of SRAM-based FPGAs, namely
Partial Dynamic Reconfiguration, to improve the resilience of critical systems that take …

[PDF][PDF] Research on fault injection system of FPGA in irradiation environment

X Xiaoliang, S Haibing, S Huailiang… - Opto-Electronic …, 2019 - researching.cn
This article studied the frame structure of Xilinx FPGA configuration RAM, giving the method
of extracting the frame structure and providing the order of frames in the bit stream file. The …

Delay monitor circuit for sensitive nodes in SRAM-Based FPGA

M Darvishi, Y Audet, Y Blaquiere - arXiv preprint arXiv:1807.11311, 2018 - arxiv.org
Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA Page 1 2017 IEEE Nuclear
and Space Radiation Effects Conference, July 17-21, 2017 – New Orleans, Louisiana, USA 1 …

System-on-chip based diverse redundancy for automotive reliability

OM Hiari - 2015 - search.proquest.com
The continuous requirement to provide low-cost, and compact systems in automotive
applications exposes the implementations to increasing types of faults. As systems become …