TEA-RC: Thread Context-Aware Register Cache for GPUs

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[HTML][HTML] Incorporation of adaptive compression into a GPU parallel computing framework for analyzing large-scale vessel trajectories

Y Li, H Li, C Zhang, Y Zhao, Z Yang - Transportation Research Part C …, 2024 - Elsevier
Abstract Automatic Identification System (AIS) offers a wealth of vessel navigation data,
which underpins research in maritime data mining, situational awareness, and knowledge …
被引用次数：5 相关文章 所有 2 个版本

A Survey on Heterogeneous CPU–GPU Architectures and Simulators

M Alaei, F Yazdanpanah - Concurrency and Computation …, 2024 - Wiley Online Library
Heterogeneous architectures are vastly used in various high performance computing
systems from IoT‐based embedded architectures to edge and cloud systems. Although …
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Conflict-aware compiler for hierarchical register file on GPUs

E Jeong, ES Park, G Koo, Y Oh, MK Yoon - Journal of Systems Architecture, 2024 - Elsevier
Modern graphics processing units (GPUs) leverage a high degree of thread-level
parallelism, necessitating large-sized register files for storing numerous thread contexts. To …
相关文章 所有 2 个版本