This paper presents a comprehensive survey on global routing research over about the last
two decades, with an emphasis on the problems of simultaneously routing multiple nets in …

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become
one of the most popular implementation media for digital circuits and have grown into a $2 …

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Interconnect power is dynamic power dissipation due to switching of interconnection
capacitances. This paper describes the characterization of interconnect power in a state-of …

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS
circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach …

The driving force behind the spectacular advancement of the integrated circuit technology in
the past thirty years has been the exponential scaling of the feature size, ie, the minimum …

Closed form solutions for the 50% delay, rise time, overshoots, and settling time of signals in
an RLC tree are presented. These solutions have the same accuracy characteristics as the …

This paper concerns a method for digital circuit optimization based on formulating the
problem as a geometric program (GP) or generalized geometric program (GGP), which can …

Most recent class-level object recognition systems work with visual words, ie, vector
quantized local descriptors. In this paper we examine the feasibility of a data-independent …

Buffer insertion has successfully been applied to reduce delay in global interconnect paths;
however, existing techniques only optimize delay and timing slack. With the increasing ratio …