Brief overview of the impact of thermal stress on the reliability of through silicon via: Analysis, characterization, and enhancement
S Tang, J Chen, YB Hu, C Yu, H Lu, S Zhang… - Materials Science in …, 2024 - Elsevier
Abstract Three-dimensional (3D) integration is considered an effective approach to extend
and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides …
and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides …
Fatigue behaviour analysis of thermal cyclic loading for through-silicon via structures based on backstress stored energy density
H Qian, Z Huang, H Fan, Y Wang, L Cao, Q Zhu… - International Journal of …, 2024 - Elsevier
Through-silicon via (TSV) structures are widely used in microelectronic due to the ease of
chip interconnection. Few research has focused on investigating the fatigue properties of …
chip interconnection. Few research has focused on investigating the fatigue properties of …
Research on Crystal Structure Evolution and Failure Mechanism during TSV-Metal Line Electromigration Process
T Gong, L Xie, S Chen, X Lu, M Zhao, J Zhu, X Yang… - Crystals, 2023 - mdpi.com
The combined use of Through Silicon Via (TSV) and metal lines, referred to as TSV-metal
lines, is an essential structure in three-dimensional integrated circuits. In-depth research into …
lines, is an essential structure in three-dimensional integrated circuits. In-depth research into …
3d Package Thermal Analysis and Thermal Optimization
Y Deng, P Liu, P Xu, L Yan, Z Zhang, J Jin - Available at SSRN 4829230 - papers.ssrn.com
Abstract 3D packaging mainly uses TSVs (Through Silicon via) to vertically interconnect
multiple chips, achieving the purpose of signal transmission and electrical connection. As a …
multiple chips, achieving the purpose of signal transmission and electrical connection. As a …