Transistor device and method of manufacturing such a transistor device
S Nuttinck, G Curatola - US Patent 8,362,561, 2013 - Google Patents
A FinFET (= Fin Field Effect Transistor) may provide a proper drive current and may avoid so-
called short-channel effects that limit the performance of a FET. US Pat. No. 6,413,802 …
called short-channel effects that limit the performance of a FET. US Pat. No. 6,413,802 …
Tri-gate devices and methods of fabrication
RS Chau, BS Doyle, J Kavalieros, D Barlage… - US Patent …, 2008 - Google Patents
4,906,589 A 3, 1990 Chao 4,996,574 A 2f1991 Shirasaki et al. 5,124,777 A 6, 1992 Lee
5,338,959 A 8, 1994 Kim et al. 5,346,839 A 9, 1994 Sundaresan................. 438/164 …
5,338,959 A 8, 1994 Kim et al. 5,346,839 A 9, 1994 Sundaresan................. 438/164 …
Method of forming a metal oxide dielectric
JK Brask, BS Doyle, J Kavalleros, M Doczy… - US Patent …, 2008 - Google Patents
(57) ABSTRACT A semiconductor device comprising a semiconductor body having a top
surface and a first and second laterally opposite sidewalls as formed on an insulating …
surface and a first and second laterally opposite sidewalls as formed on an insulating …
Nonplanar transistors with metal gate electrodes
JK Brask, BS Doyle, ML Doczy, RS Chau - US Patent 7,105,390, 2006 - Google Patents
(57) ABSTRACT A semiconductor device comprising a semiconductor body having a top
Surface and a first and second laterally opposite sidewalls as formed on an insulating …
Surface and a first and second laterally opposite sidewalls as formed on an insulating …
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
SA Hareland, RS Chau, BS Doyle, R Rios… - US Patent …, 2010 - Google Patents
A nonplanar semiconductor device and its method of fabrication is described. The nonplanar
semiconductor device includes a semiconductor body having a top surface opposite a …
semiconductor device includes a semiconductor body having a top surface opposite a …
CMOS devices with a single work function gate electrode and method of fabrication
B Doyle, BY Jin, J Kavalieros, S Datta… - US Patent App. 11 …, 2007 - Google Patents
Described herein are a device utilizing a gate electrode material with a single work function
for both the pMOS and nMOS transistors where the magnitude of the transistor threshold …
for both the pMOS and nMOS transistors where the magnitude of the transistor threshold …
Method and apparatus for improving stability of a 6T CMOS SRAM cell
S Datta, BS Doyle, RS Chau, J Kavalieros… - US Patent …, 2005 - Google Patents
US6970373B2 - Method and apparatus for improving stability of a 6T CMOS SRAM cell -
Google Patents US6970373B2 - Method and apparatus for improving stability of a 6T CMOS …
Google Patents US6970373B2 - Method and apparatus for improving stability of a 6T CMOS …
Tri-gate devices and methods of fabrication
RS Chau, BS Doyle, J Kavalieros, D Barlage… - US Patent …, 2005 - Google Patents
The present invention is a semiconductor device comprising a semiconductor body having a
top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is …
top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is …
Transistor having three electrically isolated electrodes and method of formation
L Mathew, R Muralidhar - US Patent 7,098,502, 2006 - Google Patents
A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three
gate regions may be electrically biased differently and the gate regions may have different …
gate regions may be electrically biased differently and the gate regions may have different …
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
N Lindert, SM Cea - US Patent 7,154,118, 2006 - Google Patents
A method of a bulk tri-gate transistor having stained enhanced mobility and its method of
fabrication. The present invention is a nonplanar transistor having a strained enhanced …
fabrication. The present invention is a nonplanar transistor having a strained enhanced …