FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review

AA Yazdeen, SRM Zeebaree… - Qubahan Academic …, 2021 - journal.qubahan.com
In recent days, increasing numbers of Internet and wireless network users have helped
accelerate the need for encryption mechanisms and devices to protect user data sharing …

VLSI design of Advanced-Features AES CryptoProcessor in the framework of the European Processor Initiative

P Nannipieri, S Di Matteo, L Baldanzi… - … Transactions on Very …, 2021 - ieeexplore.ieee.org
This article presents a cryptographic hardware (HW) accelerator supporting multiple
advanced encryption standard (AES)-based block cipher modes, including the more …

Trace alignment preprocessing in side-channel analysis using the adaptive filter

S Gu, Z Luo, Y Chu, Y Xu, Y Jiang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Trace alignment can improve the subsequent side-channel analysis against the trace. Most
current trace alignment schemes are, however, typically operated under a high signal-to …

Correlation power analysis attack resisted cryptographic RISC-V SoC with random dynamic frequency scaling countermeasure

BA Dao, TT Hoang, AT Le, A Tsukamoto… - IEEE …, 2021 - ieeexplore.ieee.org
Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these
systems, cryptographic accelerators are integrated with processor cores to provide users …

Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC

TH Tran, BA Dao, DH Le, VP Hoang… - … Transactions on Very …, 2024 - ieeexplore.ieee.org
Side-channel analysis attacks have become the primary method for exploiting the
vulnerabilities of cryptographic devices. Therefore, focusing on countermeasures to …

Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm

TH Tran, DT Dam, BA Dao, VP Hoang… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
Nowadays, cryptographic algorithms are widely used to build safety mechanisms for specific
objects in security services. Nevertheless, these algorithms are implemented in the …

Using Non-Autonomous Chaotic Clocks to Drive CPA-Resistant AES Cryptographic Chips

AA El-Moursy, AM Darya, S Majzoub… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this brief, we provide further evidence on the robustness of the chaotic clocking technique
for driving a Correlation Power Analysis (CPA) resistant cryptographic chip running the …

Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks

V Padmakumar, TM Ignatius, TB Singha… - IEEE Embedded …, 2024 - ieeexplore.ieee.org
Advanced Encryption Standard's (AES) vulnerabilities surfaced with Power Side Channel
Attacks (PSCA). Enhancing security by adding extra countermeasure circuitry introduces …

A Novel Clock Randomization Method Against Side-channel Attack

J Yu, Z Wang, B Shan, X Wang - International Conference on Computer …, 2022 - Springer
Abstract Side-Channel Attack (SCA) has become a major concern in the protection of secret
data processed in cryptographic devices. As a main direction of hardware countermeasures …

Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks

TH Tran, AT Le, TT Hoang, VP Hoang… - Proceedings of the Great …, 2023 - dl.acm.org
Research on side-channel attacks has recently made a lot of progress, and one of the most
potential solutions is a power analysis attack. Thus, focusing on countermeasures to …