A new design technique for sub-nanosecond delay and 200 V/ns power supply slew-tolerant floating voltage level shifters for GaN SMPS
Dual-output gate drivers for switched-mode power supplies require low-side reference
signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN …
signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN …
An 18 V input 10 MHz buck converter with 125 ps mixed-signal dead time control
J Wittmann, A Barner, T Rosahl… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A highly integrated synchronous buck converter with a predictive dead time control for input
voltages> 18 V with 10 MHz switching frequency is presented. A high resolution dead time …
voltages> 18 V with 10 MHz switching frequency is presented. A high resolution dead time …
Design of 370-ps delay floating-voltage level shifters with 30-V/ns power supply slew tolerance
A new design method for producing high-performance and power-rail slew-tolerant floating-
voltage level shifters is presented, offering increased speed, reduced power consumption …
voltage level shifters is presented, offering increased speed, reduced power consumption …
A versatile SoC/SiP sensor interface for industrial applications: Implementation challenges
We present in this paper design considerations and implementation challenges of a
proposed versatile SoC/SiP sensor interface intended for industrial applications. The …
proposed versatile SoC/SiP sensor interface intended for industrial applications. The …
Enhanced dynamic regulation in Buck Converters: integrating input-voltage feedforward with voltage-mode feedback
DC-DC buck converters in automotive and aerospace applications are often required to
handle large disturbances in their input supply and abrupt variations in their loads. This …
handle large disturbances in their input supply and abrupt variations in their loads. This …
A versatile SoC/SiP sensor interface for industrial applications: Design considerations
This paper presents design considerations and implementation challenges of a proposed
versatile SoC/SiP sensor interface intended for industrial applications. The proposed …
versatile SoC/SiP sensor interface intended for industrial applications. The proposed …
A Half-bridge Gate Driver with Self-adjusting and Tunable Dead-time Modes for Efficient Switched-mode Power Systems
The design of high-voltage (HV) switched-mode power systems (SMPSys) poses multiple
challenges, such as minimizing the switching losses and preventing possible shoot-through …
challenges, such as minimizing the switching losses and preventing possible shoot-through …
A multiphase class-D automotive audio amplifier with integrated low-latency ADCs for digitized feedback after the output filter
D Schinkel, W Groothedde, F Mostert… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
A 5× 80 W class-D audio power amplifier for automotive applications is presented. The
amplifier is implemented in a 140-nm bipolar CMOS DMOS SOI. Configurable digital-loop …
amplifier is implemented in a 140-nm bipolar CMOS DMOS SOI. Configurable digital-loop …
A W Monolithic Five-Level Class-D Audio Power Amplifier in 180 nm BCD
M Høyerby, JK Jakobsen, J Midtgaard… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A 2× 70 W from 24 V into 4 Ω class-D audio power amplifier in 30/40 V 180 nm bipolar
CMOS DMOS is presented. The device employs a flying capacitor (FC) three-level half …
CMOS DMOS is presented. The device employs a flying capacitor (FC) three-level half …
Design of multioctave high-efficiency power amplifiers using stochastic reduced order models
This paper presents a novel general design method of frequency varying impedance
matching. The method is applied to design of a broadband high-efficiency power amplifier …
matching. The method is applied to design of a broadband high-efficiency power amplifier …