Low-power pulse-triggered flip-flop design based on a signal feed-through
JF Lin - IEEE transactions on very large scale integration (vlsi) …, 2013 - ieeexplore.ieee.org
In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered
structure and a modified true single phase clock latch based on a signal feed-through …
structure and a modified true single phase clock latch based on a signal feed-through …
Design of sequential elements for low power clocking system
Power consumption is a major bottleneck of system performance and is listed as one of the
top three challenges in International Technology Roadmap for Semiconductor 2008. In …
top three challenges in International Technology Roadmap for Semiconductor 2008. In …
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power
The power efficiency and reducing the layout area are two main concerns in D-Flip-Flops (D-
FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the …
FF) design. In this paper, a novel architecture is presented for the pulse-triggered D-FF in the …
Comparative analysis and study of metastability on high-performance flip-flops
In this paper, we analyze and characterize the metastability of 11 previously proposed high-
performance flip-flops, reduced clock-swing flip-flops, and level-converting flip-flops. From …
performance flip-flops, reduced clock-swing flip-flops, and level-converting flip-flops. From …
An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive
scaling down of the input voltage. In this paper, we proposed a wide output range level …
scaling down of the input voltage. In this paper, we proposed a wide output range level …
Low-power redundant-transition-free TSPC dual-edge-triggering flip-flop using single-transistor-clocked buffer
In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has
become one of the most power-hungry blocks in processors. To address this issue, a novel …
become one of the most power-hungry blocks in processors. To address this issue, a novel …
An ultra-low-voltage level shifter with embedded re-configurable logic and time-borrowing latch technique
The increasing number of voltage domains along with the size of the data bus requires an
exponential increase in the number level shifter (LS) circuits for signal interfacing, creating …
exponential increase in the number level shifter (LS) circuits for signal interfacing, creating …
Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic
L Boggarapu, SPK K, B Lakshmi - International Journal of …, 2023 - Taylor & Francis
This work explores homo-and heterojunction tunnel field-effect transistor (TFET)-based
NAND and NOR logic circuits using 30 nm technology and compares their performance in …
NAND and NOR logic circuits using 30 nm technology and compares their performance in …
Low-power level converting flip-flop with a conditional clock technique in dual supply systems
J Shen, L Geng, G Xiang, J Liang - Microelectronics journal, 2014 - Elsevier
Clustered voltage scaling (CVS) is an effective way to reduce power consumption in digital
integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In …
integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In …
[HTML][HTML] Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology
The interest in alternative logic technologies is continuously increasing for short nanometer
designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene …
designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene …