Recent advances and trends in advanced packaging

JH Lau - IEEE Transactions on Components, Packaging and …, 2022 - ieeexplore.ieee.org
In this study, advanced packaging is defined. The kinds of advanced packaging are ranked
based on their interconnect density and electrical performance, and are grouped into 2-D …

Co-packaged photonics for high performance computing: status, challenges and opportunities

R Mahajan, X Li, J Fryman, Z Zhang… - Journal of Lightwave …, 2021 - ieeexplore.ieee.org
Photonics die or integrated photonics modules co-packaged with compute engines have the
potential to deliver significant improvements in power, bandwidth and reach needed to meet …

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors

R Pendurthi, NU Sakib, MUK Sadaf, Z Zhang… - Nature …, 2024 - nature.com
The semiconductor industry is transitioning to the 'More Moore'era, driven by the adoption of
three-dimensional (3D) integration schemes surpassing the limitations of traditional two …

Three-dimensional integration of two-dimensional field-effect transistors

D Jayachandran, R Pendurthi, MUK Sadaf, NU Sakib… - Nature, 2024 - nature.com
In the field of semiconductors, three-dimensional (3D) integration not only enables
packaging of more devices per unit area, referred to as 'More Moore'but also introduces …

[图书][B] Advanced packaging

JH Lau, JH Lau - 2021 - Springer
First of all, semiconductor technology is out of the scope of this book and semiconductor
advanced packaging technology is the focus. In this chapter, the advanced packaging will …

[HTML][HTML] Challenges and recent prospectives of 3D heterogeneous integration

S Zhang, Z Li, H Zhou, R Li, S Wang, KW Paik… - E-Prime-Advances in …, 2022 - Elsevier
With the continuous reduction of chip feature size, the continuation of Moore's Law becomes
increasingly difficult and heterogeneous integration has become one of the important …

Power delivery for high-performance microprocessors—challenges, solutions, and future trends

K Radhakrishnan, M Swaminathan… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
The power delivery requirements for the early microprocessors were fairly rudimentary due
to the relatively low power levels. However, several decades of exponential scaling powered …

Ponte Vecchio: A multi-tile 3D stacked processor for exascale computing

W Gomes, A Koker, P Stover, D Ingerly… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
Ponte Vecchio (PVC) is a heterogenous petaop 3D processor comprising 47 functional tiles
on five process nodes. The tiles are connected with Foveros [1] and EMIB [2] to operate as a …

2.5 D and 3D heterogeneous integration: Emerging applications

F Sheikh, R Nagisetty, T Karnik… - IEEE Solid-State Circuits …, 2021 - ieeexplore.ieee.org
The next decade will usher in a new era of technological innovation where compute,
communications, and intelligence will converge. The number of connected devices is …

8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package

W Gomes, S Khushu, DB Ingerly… - … Solid-State Circuits …, 2020 - ieeexplore.ieee.org
The Lakefield processor combines heterogeneous 3D die stacking also called Foveros, with
hybrid computing to enable a new class of small form factor mobile products. The stacked …