Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study
Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-
around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects …
around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects …
Simulation study on ferroelectric layer thickness dependence RF/Analog and linearity parameters in ferroelectric tunnel junction TFET
R Saha - Microelectronics Journal, 2021 - Elsevier
In this paper, the impact of ferroelectric layer thickness (t FE) on input drain current
characteristic is reported in ferroelectric tunnel junction (FTJ) TFET through TCAD simulator …
characteristic is reported in ferroelectric tunnel junction (FTJ) TFET through TCAD simulator …
Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor
In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is
proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function …
proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function …
Impact of temperature on the reliability of UTB-DG-FE-TFETs and their RF/analog and linearity parameter dependence
This study aimed to investigate the influence of temperature on the reliability of an ultrathin-
body double-gate ferroelectric tunnel field-effect transistor (UTB-DG-FE-TFET). An in-depth …
body double-gate ferroelectric tunnel field-effect transistor (UTB-DG-FE-TFET). An in-depth …
Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET
In this paper, the electrical parameters are evaluated for the variations of temperature in
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …
Impact of band gap and gate dielectric engineering on novel Si0. 1Ge0. 9-GaAs lateral N-type charge plasma based JLTFET
K Kumar, SC Sharma - Microelectronics Journal, 2022 - Elsevier
In this research article, a device called dual dielectric gate hetero-material junctionless TFET
(DD-HJLTFET) is proposed using a novel amalgamation of Si 0.1 Ge 0.9/GaAs for the first …
(DD-HJLTFET) is proposed using a novel amalgamation of Si 0.1 Ge 0.9/GaAs for the first …
Impact on performance of dual stack hetero-gated dielectric modulated TFET biosensor due to Si1-xGex pocket variation
In this work, the performance evaluation of a dual stack hetero-gated pocket modulated
tunnel FET (DSHGPM-TFET) based biosensor is presented. In the proposed device, cavity is …
tunnel FET (DSHGPM-TFET) based biosensor is presented. In the proposed device, cavity is …
Design and analysis of a dual gate tunnel FET with InGaAs source pockets for improved performance
In this work, we propose a novel dual gate tunnel FET (TFET) with an improved ON current.
The source pockets of the proposed TFET are designed with a narrow bandgap InGaAs …
The source pockets of the proposed TFET are designed with a narrow bandgap InGaAs …
Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique
In this paper, a comparative analysis of ambipolarity suppression in conventional PNPN-
TFET (D-1) is studied using TCAD simulation. By replacing the drain with metal silicide, and …
TFET (D-1) is studied using TCAD simulation. By replacing the drain with metal silicide, and …
On the design of p-channel step-FinFET at sub-10nm node: a parametric analysis
This paper presents a three dimensional (3-D) statistical simulation study of a 7 nm
technology node SOI p-channel step-FinFET and compares with that of a conventional …
technology node SOI p-channel step-FinFET and compares with that of a conventional …