Fidelity: Efficient resilience analysis framework for deep learning accelerators
We present a resilience analysis framework, called FIdelity, to accurately and quickly
analyze the behavior of hardware errors in deep learning accelerators. Our framework …
analyze the behavior of hardware errors in deep learning accelerators. Our framework …
[HTML][HTML] Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era
This paper discusses principles and techniques to evaluate processors for dependable
computing in space applications. The focus is on soft errors, which dominate the failure rate …
computing in space applications. The focus is on soft errors, which dominate the failure rate …
Thales: Formulating and estimating architectural vulnerability factors for dnn accelerators
As Deep Neural Networks (DNNs) are increasingly deployed in safety critical and privacy
sensitive applications such as autonomous driving and biometric authentication, it is critical …
sensitive applications such as autonomous driving and biometric authentication, it is critical …
A quatro-based 65-nm flip-flop circuit for soft-error resilience
A flip-flop circuit hardened against soft errors is presented in this paper. This design is an
improved version of Quatro for further enhanced soft-error resilience by integrating the guard …
improved version of Quatro for further enhanced soft-error resilience by integrating the guard …
Impact of technology scaling on the combinational logic soft error rate
NN Mahatme, NJ Gaspard, T Assis… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk
technology circuits operating in the GHz range suggest that the combinational logic soft error …
technology circuits operating in the GHz range suggest that the combinational logic soft error …
Radiation tolerant multi-bit flip-flop system with embedded timing pre-error sensing
A Jain, AM Veggetti, D Crippa… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents the design, implementation methodology, and validation of a multi-bit
flip-flop (FF) system that provides tolerance against single-event upsets (SEUs) and single …
flip-flop (FF) system that provides tolerance against single-event upsets (SEUs) and single …
Impact of supply voltage and frequency on the soft error rate of logic circuits
NN Mahatme, NJ Gaspard… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
Alpha particle irradiations of 28-nm combinational logic and flip-flop circuits under different
supply voltage and frequency operating conditions are investigated. Results indicate that …
supply voltage and frequency operating conditions are investigated. Results indicate that …
Technology scaling comparison of flip-flop heavy-ion single-event upset cross sections
NJ Gaspard, S Jagannathan, ZJ Diggins… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are
used to quantify single-event upset trends. The results show that as technologies scale, D …
used to quantify single-event upset trends. The results show that as technologies scale, D …
An SEU-tolerant DICE latch design with feedback transistors
This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with
both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve …
both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve …
Effects of threshold voltage variations on single-event upset response of sequential circuits at advanced technology nodes
Threshold voltage (VT) of transistors plays an important role in single-event upsets (SEU)
and system power consumption. Effect of VT on single-event upsets can be very different for …
and system power consumption. Effect of VT on single-event upsets can be very different for …