Programming memory cells with concurrent storage of multi-level data as single-level data for power loss protection

X Yang, T Miwa, K Oowada, GJ Hemink - US Patent 11,551,781, 2023 - Google Patents
Apparatuses and techniques are described for programming data in memory cells while
concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to …

Concurrent programming of multiple cells for non-volatile memory devices

X Yang, GJ Hemink, K Oowada, T Miwa - US Patent 11,545,221, 2023 - Google Patents
Technology is disclosed herein for concurrently program ming the same data pattern in
multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with …

Memory apparatus and method of operation using triple string concurrent programming during erase

X Yang, Y Song, F Wu - US Patent 11,423,996, 2022 - Google Patents
A memory apparatus and method of operation is provided. The apparatus includes a block
of memory cells. Each of the memory cells is connected to one of a plurality of word lines …

Performance of non data word line maintenance in sub block mode

S Bhatnagar, S Mishra, H Golechchha - US Patent 10,832,790, 2020 - Google Patents
A storage device may include a controller performing non data word line (NDWL)
maintenance in sub block mode (SBM). The NDWL maintenance in SBM can include …

Read techniques to reduce read errors in a memory device

J Guo, X Yang - US Patent 11,972,806, 2024 - Google Patents
The memory device includes a memory block with a plurality of memory cells, which are
programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control …

NAND flash memory device and method of reducing program disturb thereof

H Liu, D Huang, W Wei, Y Huang - US Patent 12,009,036, 2024 - Google Patents
In certain aspects, a memory device includes memory strings each including a drain select
gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory …

Programming memory cells with concurrent redundant storage of data for power loss protection

X Yang, T Miwa, K Oowada, GJ Hemink - US Patent 11,625,172, 2023 - Google Patents
US11625172B2 - Programming memory cells with concurrent redundant storage of data for
power loss protection - Google Patents US11625172B2 - Programming memory cells with …

Efficient handling of background operations for improving sustained performance of host reads and writes

SP Gunda, Y Chandranna - US Patent 11,797,228, 2023 - Google Patents
A data storage device including, in one implementation, a non-volatile memory device
having a memory block including a number of memory dies, and a controller coupled to the …

3D NAND flash and operation method thereof

H Liu, D Huang, W Wei, Y Huang - US Patent 11,177,001, 2021 - Google Patents
A programming method of an increment step pulse program (ISPP) for a three-dimension
(3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D …

Concurrent programming of multiple cells for non-volatile memory devices

X Yang, A Lee, GJ Hemink, K Oowada… - US Patent 11,342,028, 2022 - Google Patents
Apparatuses, systems, and methods are disclosed for concurrently programming non-
volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells …