Apparatuses and techniques are described for programming data in memory cells while
concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to …

Technology is disclosed herein for concurrently program ming the same data pattern in
multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with …

A memory apparatus and method of operation is provided. The apparatus includes a block
of memory cells. Each of the memory cells is connected to one of a plurality of word lines …

A storage device may include a controller performing non data word line (NDWL)
maintenance in sub block mode (SBM). The NDWL maintenance in SBM can include …

The memory device includes a memory block with a plurality of memory cells, which are
programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control …

In certain aspects, a memory device includes memory strings each including a drain select
gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory …

US11625172B2 - Programming memory cells with concurrent redundant storage of data for
power loss protection - Google Patents US11625172B2 - Programming memory cells with …

A data storage device including, in one implementation, a non-volatile memory device
having a memory block including a number of memory dies, and a controller coupled to the …

A programming method of an increment step pulse program (ISPP) for a three-dimension
(3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D …

Apparatuses, systems, and methods are disclosed for concurrently programming non-
volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells …