[图书][B] Binary decision diagrams: theory and implementation

R Drechsler, B Becker - 2013 - books.google.com
For someone with a hammer the whole world looks like a nail. Within the last 10-13 years
Binar· y Decision Diagmms (BDDs) have become the state-of-the-art data structure in VLSI …

SAT-based verification without state space traversal

P Bjesse, K Claessen - International Conference on Formal Methods in …, 2000 - Springer
Abstract Binary Decision Diagrams (BDD s) have dominated the area of symbolic model
checking for the past decade. Recently, the use of satisfiability (SAT) solvers has emerged …

[图书][B] Logic synthesis and verification

S Hassoun, T Sasao - 2001 - books.google.com
Research and development of logic synthesis and verification have matured considerably
over the past two decades. Many commercial products are available, and they have been …

[图书][B] Decision diagram techniques for micro-and nanoelectronic design handbook

SN Yanushkevich, DM Miller, VP Shmerko… - 2018 - taylorfrancis.com
Decision diagram (DD) techniques are very popular in the electronic design automation
(EDA) of integrated circuits, and for good reason. They can accurately simulate logic design …

Binary decision diagrams

RE Bryant - Handbook of model checking, 2018 - Springer
Binary decision diagrams provide a data structure for representing and manipulating
Boolean functions in symbolic form. They have been especially effective as the algorithmic …

BDD-based logic synthesis for LUT-based FPGAs

N Vemuri, P Kalla, R Tessier - ACM Transactions on Design Automation …, 2002 - dl.acm.org
Contemporary FPGA synthesis is a multiphase process that involves technology-
independent logic optimization followed by FPGA-specific mapping to a target FPGA …

Human-robot interaction: Engagement between humans and robots for hosting activities

CL Sidner, M Dzikovska - Proceedings. fourth ieee international …, 2002 - ieeexplore.ieee.org
To participate in conversations with people, robots must not only see and talk to people, but
must also make use of the conventions of conversation and connection to their human …

Achieving scalability in parallel reachability analysis of very large circuits

T Heyman, D Geist, O Grumberg, A Schuster - … , IL, USA, July 15-19, 2000 …, 2000 - Springer
This paper presents a scalable method for parallel symbolic reachability analysis on a
distributed-memory environment of workstations. Our method makes use of an adaptive …

Taylor expansion diagrams: A canonical representation for verification of data flow designs

M Ciesielski, P Kalla, S Askar - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
A Taylor expansion diagram (TED) is a compact, word-level, canonical representation for
data flow computations that can be expressed as multivariate polynomials. TEDs are based …

Reachability analysis using partitioned-ROBDDs

Narayan, Isles, Jain, Brayton - 1997 Proceedings of IEEE …, 1997 - ieeexplore.ieee.org
We address the problem of finite state machine (FSM) traversal, a key step in most
sequential verification and synthesis algorithms. We propose the use of partitioned ROBDDs …