Data processing systems
J Nystad - US Patent 10,176,546, 2019 - Google Patents
(57) ABSTRACT A data processing system determines for a stream of instruc tions to be
executed, whether there are any instructions that can be re-ordered in the instruction stream …
executed, whether there are any instructions that can be re-ordered in the instruction stream …
Error handling during onboarding of a service
W Johnson, S Dastouri, I Liu - US Patent 10,908,984, 2021 - Google Patents
US10908984B2 - Error handling during onboarding of a service - Google Patents US10908984B2
- Error handling during onboarding of a service - Google Patents Error handling during …
- Error handling during onboarding of a service - Google Patents Error handling during …
Onboarding of a service based on automated supervision of task completion
W Johnson, S Dastouri, I Liu - US Patent 11,256,542, 2022 - Google Patents
Described herein are techniques and systems for onboarding a service from client-managed
computing infrastructure to network computing infrastructure. As part of the onboard ing, a …
computing infrastructure to network computing infrastructure. As part of the onboard ing, a …
Method of managing task dependencies at runtime in a parallel computing system of a hardware processing system and a hardware acceleration processor
X Tan, CA Martinez, JB Pons, DJ Gonzalez… - US Patent …, 2022 - Google Patents
Hardware acceleration of task dependency management in parallel computing, wherein
solutions are proposed for hardware-based dependency management to support nested …
solutions are proposed for hardware-based dependency management to support nested …
Path prediction method used for instruction cache, access control unit, and instruction processing apparatus
D Liu, T Jiang, C Chen - US Patent 11,720,365, 2023 - Google Patents
An instruction processing apparatus is disclosed and includes: an instruction cache, which
maps data blocks in a memory based on a multi-way set-associative structure and includes …
maps data blocks in a memory based on a multi-way set-associative structure and includes …
Deadlock free resource management in block based computing architectures
VRK Naresh, GM WRIGHT - US Patent 10,783,011, 2020 - Google Patents
Abstract Systems and methods are directed to efficient management of processor resources,
particularly General Purpose Registers (GPRs), for example to minimize pipeline flushes …
particularly General Purpose Registers (GPRs), for example to minimize pipeline flushes …
Apparatus and method for processing a plurality of tasks
B Saballus, E Ott, J Friedrich, J Bregenzer… - US Patent …, 2019 - Google Patents
An apparatus and a method for processing a plurality of tasks in cycles on a plurality of
computation cores, provision being made also to determine, within one cycle for processing …
computation cores, provision being made also to determine, within one cycle for processing …