Pre-charge voltage for inhibiting unselected NAND memory cell programming
X Yang - US Patent 10,726,920, 2020 - Google Patents
Techniques are provided for pre-charging NAND strings during a programming operation.
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …
Interleaved program and verify in non-volatile memory
X Yang, HY Tseng, D Dutta - US Patent 10,643,721, 2020 - Google Patents
A circuit includes a program controller configured to perform a program operation with
interleaved program-verify loops to program memory cells in a same block. During each …
interleaved program-verify loops to program memory cells in a same block. During each …
Semiconductor memory device
K Kimura, M Iga, Y Suzuki - US Patent 10,490,278, 2019 - Google Patents
According to one embodiment, a semiconductor memory device includes a memory string
including a first select transistor, a first transistor adjacent to the first select transistor, and a …
including a first select transistor, a first transistor adjacent to the first select transistor, and a …
Asymmetric voltage ramp rate control
X Yang, HY Tseng, D Dutta - US Patent 10,468,111, 2019 - Google Patents
Abstract Systems and methods reduce device peak current during a read operation by
charging control lines of a first set of memory cells faster than control lines of a second set of …
charging control lines of a first set of memory cells faster than control lines of a second set of …
Managing bit-line settling time in non-volatile memory
YC Lien, X Yang, Z Zhou, D Dutta - US Patent 10,636,498, 2020 - Google Patents
A non-volatile memory system comprises a plurality of word lines, a plurality of bit lines, non-
volatile memory cells, and a sensing circuit. The sensing circuit is configured to sense a first …
volatile memory cells, and a sensing circuit. The sensing circuit is configured to sense a first …
Memory disturb detection
X Yang, HY Tseng, D Dutta - US Patent 10,839,922, 2020 - Google Patents
An apparatus includes an array of memory cells comprising a first sub-block and a second
sub-block electrically coupled by a channel. The apparatus also includes a measurement …
sub-block electrically coupled by a channel. The apparatus also includes a measurement …
Transistor threshold voltage maintenance in 3D memory
S Seetharaman, P Sagdeo, S Sankule… - US Patent 10,691,372, 2020 - Google Patents
Techniques are provided for maintaining threshold voltages of non-data transistors in a
memory device. The memory device has a stack comprising alternating horizontal …
memory device. The memory device has a stack comprising alternating horizontal …
Dynamic allocation of sub blocks
S Mishra, H Golechchha, S Bhatnagar - US Patent 11,287,989, 2022 - Google Patents
(57) ABSTRACT A system, apparatus, and method for dynamic allocation of sub-blocks.
First, a non-volatile memory array receives a set of write commands. The non-volatile …
First, a non-volatile memory array receives a set of write commands. The non-volatile …
Pre-charge voltage for inhibiting unselected NAND memory cell programming
X Yang - US Patent 11,081,179, 2021 - Google Patents
Techniques are provided for pre-charging NAND strings during a programming operation.
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …
Interleaved program and verify in non-volatile memory
X Yang, HY Tseng, D Dutta - US Patent 10,885,994, 2021 - Google Patents
(57) ABSTRACT A circuit includes a program controller configured to per form a program
operation with interleaved program-verify loops to program memory cells in a same block …
operation with interleaved program-verify loops to program memory cells in a same block …