Techniques are provided for pre-charging NAND strings during a programming operation.
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …

A circuit includes a program controller configured to perform a program operation with
interleaved program-verify loops to program memory cells in a same block. During each …

According to one embodiment, a semiconductor memory device includes a memory string
including a first select transistor, a first transistor adjacent to the first select transistor, and a …

Abstract Systems and methods reduce device peak current during a read operation by
charging control lines of a first set of memory cells faster than control lines of a second set of …

A non-volatile memory system comprises a plurality of word lines, a plurality of bit lines, non-
volatile memory cells, and a sensing circuit. The sensing circuit is configured to sense a first …

An apparatus includes an array of memory cells comprising a first sub-block and a second
sub-block electrically coupled by a channel. The apparatus also includes a measurement …

Techniques are provided for maintaining threshold voltages of non-data transistors in a
memory device. The memory device has a stack comprising alternating horizontal …

(57) ABSTRACT A system, apparatus, and method for dynamic allocation of sub-blocks.
First, a non-volatile memory array receives a set of write commands. The non-volatile …

Techniques are provided for pre-charging NAND strings during a programming operation.
The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge …

(57) ABSTRACT A circuit includes a program controller configured to per form a program
operation with interleaved program-verify loops to program memory cells in a same block …