[PDF][PDF] Adapting Software Fault Isolation to Contemporary {CPU} Architectures

D Sehr, R Muth, C Biffle, V Khimenko, E Pasko… - 19th USENIX Security …, 2010 - usenix.org
Abstract Software Fault Isolation (SFI) is an effective approach to sandboxing binary code of
questionable provenance, an interesting use case for native plugins in a Web browser. We …

Classifying memory access patterns for prefetching

G Ayers, H Litz, C Kozyrakis… - Proceedings of the Twenty …, 2020 - dl.acm.org
Prefetching is a well-studied technique for addressing the memory access stall time of
contemporary microprocessors. However, despite a large body of related work, the memory …

Globally optimal solution to multi-object tracking with merged measurements

JF Henriques, R Caseiro… - … Conference on Computer …, 2011 - ieeexplore.ieee.org
Multiple object tracking has been formulated recently as a global optimization problem, and
solved efficiently with optimal methods such as the Hungarian Algorithm. A severe limitation …

APT-GET: profile-guided timely software prefetching

S Jamilan, TA Khan, G Ayers, B Kasikci… - Proceedings of the …, 2022 - dl.acm.org
Prefetching which predicts future memory accesses and preloads them from main memory,
is a widely-adopted technique to overcome the processor-memory performance gap …

[PDF][PDF] Design and implementation of a lightweight dynamic optimization system

J Lu, H Chen, PC Yew, WC Hsu - Journal of Instruction-Level …, 2004 - researchgate.net
Many opportunities exist to improve micro-architectural performance due to performance
events that are difficult to optimize at static compile time. Cache misses and branch mis …

The performance of runtime data cache prefetching in a dynamic optimization system

J Lu, H Chen, R Fu, WC Hsu, B Othmer… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
Traditional software controlled data cache prefetching is often ineffective due to the lack of
runtime cache miss and miss address information. To overcome this limitation, we …

Propeller: A profile guided, relinking optimizer for warehouse-scale applications

H Shen, K Pszeniczny, R Lavaee, S Kumar… - Proceedings of the 28th …, 2023 - dl.acm.org
While profile guided optimizations (PGO) and link time optimiza-tions (LTO) have been
widely adopted, post link optimizations (PLO) have languished until recently when …

Ispike: a post-link optimizer for the intel/spl reg/itanium/spl reg/architecture

CK Luk, R Muth, H Patil, R Cohn… - … Symposium on Code …, 2004 - ieeexplore.ieee.org
Ispike is a post-link optimizer developed for the Intel/spl reg/Itanium Processor Family (IPF)
processors. The IPF architecture poses both opportunities and challenges to post-link …

Adaptive page migration policy with huge pages in tiered memory systems

T Heo, Y Wang, W Cui, J Huh… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
To accommodate the growing demand for memory capacity in a cost-effective way, multiple
types of memory are incorporated in a single system. In such tiered memory systems …

Prefetch injection based on hardware monitoring and object metadata

AR Adl-Tabatabai, RL Hudson, MJ Serrano… - ACM SIGPLAN …, 2004 - dl.acm.org
Cache miss stalls hurt performance because of the large gap between memory and
processor speeds-for example, the popular server benchmark SPEC JBB2000 spends 45 …