[PDF][PDF] Adapting Software Fault Isolation to Contemporary {CPU} Architectures
Abstract Software Fault Isolation (SFI) is an effective approach to sandboxing binary code of
questionable provenance, an interesting use case for native plugins in a Web browser. We …
questionable provenance, an interesting use case for native plugins in a Web browser. We …
Classifying memory access patterns for prefetching
Prefetching is a well-studied technique for addressing the memory access stall time of
contemporary microprocessors. However, despite a large body of related work, the memory …
contemporary microprocessors. However, despite a large body of related work, the memory …
Globally optimal solution to multi-object tracking with merged measurements
JF Henriques, R Caseiro… - … Conference on Computer …, 2011 - ieeexplore.ieee.org
Multiple object tracking has been formulated recently as a global optimization problem, and
solved efficiently with optimal methods such as the Hungarian Algorithm. A severe limitation …
solved efficiently with optimal methods such as the Hungarian Algorithm. A severe limitation …
APT-GET: profile-guided timely software prefetching
Prefetching which predicts future memory accesses and preloads them from main memory,
is a widely-adopted technique to overcome the processor-memory performance gap …
is a widely-adopted technique to overcome the processor-memory performance gap …
[PDF][PDF] Design and implementation of a lightweight dynamic optimization system
Many opportunities exist to improve micro-architectural performance due to performance
events that are difficult to optimize at static compile time. Cache misses and branch mis …
events that are difficult to optimize at static compile time. Cache misses and branch mis …
The performance of runtime data cache prefetching in a dynamic optimization system
Traditional software controlled data cache prefetching is often ineffective due to the lack of
runtime cache miss and miss address information. To overcome this limitation, we …
runtime cache miss and miss address information. To overcome this limitation, we …
Propeller: A profile guided, relinking optimizer for warehouse-scale applications
While profile guided optimizations (PGO) and link time optimiza-tions (LTO) have been
widely adopted, post link optimizations (PLO) have languished until recently when …
widely adopted, post link optimizations (PLO) have languished until recently when …
Ispike: a post-link optimizer for the intel/spl reg/itanium/spl reg/architecture
Ispike is a post-link optimizer developed for the Intel/spl reg/Itanium Processor Family (IPF)
processors. The IPF architecture poses both opportunities and challenges to post-link …
processors. The IPF architecture poses both opportunities and challenges to post-link …
Adaptive page migration policy with huge pages in tiered memory systems
To accommodate the growing demand for memory capacity in a cost-effective way, multiple
types of memory are incorporated in a single system. In such tiered memory systems …
types of memory are incorporated in a single system. In such tiered memory systems …
Prefetch injection based on hardware monitoring and object metadata
AR Adl-Tabatabai, RL Hudson, MJ Serrano… - ACM SIGPLAN …, 2004 - dl.acm.org
Cache miss stalls hurt performance because of the large gap between memory and
processor speeds-for example, the popular server benchmark SPEC JBB2000 spends 45 …
processor speeds-for example, the popular server benchmark SPEC JBB2000 spends 45 …