A review of new time-to-digital conversion techniques

S Tancock, E Arabul, N Dahnoun - IEEE transactions on …, 2019 - ieeexplore.ieee.org
Time-to-digital converters (TDCs) are vital components in time and distance measurement
and frequency-locking applications. There are many architectures for implementing TDCs …

[HTML][HTML] Time-to-digital conversion techniques: A survey of recent developments

J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …

[图书][B] CMOS time-mode circuits and systems: fundamentals and applications

F Yuan - 2018 - books.google.com
Time-mode circuits, where information is represented by time difference between digital
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …

All-digital successive approximation TDC in time-mode signal processing

DJ Lee, F Yuan, Y Zhou - Microelectronics Journal, 2021 - Elsevier
The need for low-power high-resolution ADCs in a broad range of emerging applications
and the architecture to realize these ADCs are examined. The pros and cons of various TDC …

The wave-union method on DSP blocks: improving FPGA-based TDC resolutions by 3x with a 1.5 x area increase

S Tancock, J Rarity, N Dahnoun - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Achieving high-resolution time-to-digital conversion is challenging at high count rates. In
past work, the highest resolutions with low dead times (≤ 2 cycles) on field-programmable …

High-precision PLL delay matrix with overclocking and double data rate for accurate FPGA time-to-digital converters

P Chen, JT Lan, RT Wang, NM Qui… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-
digital converter (TDC) with phase wrapping and averaging has been proposed recently to …

A successive approximation time-to-digital converter with single set of delay lines for time interval measurements

J Szyduczyński, D Kościelnik, M Miśkowicz - Sensors, 2019 - mdpi.com
The paper is focused on design of time-to-digital converters based on successive
approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay …

A novel 10-bit 2.8-mW TDC design using SAR with continuous disassembly algorithm

KO Ragab, H Mostafa, A Eladawy - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This brief introduces a successive approximation time-to-digital converter based on a novel
algorithm denoted as successive approximation register with continuous disassembly (SAR …

Can DSP48A1 adders be used for high-resolution delay generation?

S Tancock, E Arabul, N Dahnoun… - 2018 7th …, 2018 - ieeexplore.ieee.org
Time to digital conversion is an important task in many systems. It involves the conversion of
time-based signals (as opposed to the amplitude-based signals in analog-to-digital …

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

DJ Lee, F Yuan, GN Khan… - IET Circuits, Devices & …, 2021 - Wiley Online Library
This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and
digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond …