As technology feature sizes diminish to the nanometer regime, the leakage power crisis has
become a major challenge in network-on-chip (NoC) design. Power gating (PG) is used to …

Heterogeneous System Architectures (HSA) that integrate cores of different architectures
(CPU, GPU, etc.) on single chip are gaining significance for many class of applications to …

With increasing core counts and higher memory demands from applications, it is imperative
that networks-on-chip (NoCs) provide low-latency, power-efficient communication …

In chip-multiprocessors (CMPs) the network-on-chip (NoC) carries cache coherence and
data messages. These messages may be classified into critical and non-critical messages …

A bufferless network-on-chip (NoC) can deliver high energy efficiency, but such a NoC is
subject to growing deflection when its traffic load rises. This article proposes Deflection …

Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and
the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) …

Chip Multiprocessor Systems (CMPs) rely on a cache coherency protocol to maintain
memory access coherence between cached data and main memory. The Hammer …

Because of environmental and monetary concerns, it is increasingly important to reduce the
energy consumption in all areas, including parallel and high performance computing. In this …

In Network-on-Chip (NoC), topology is one of the most important design choices that
determine performance and power consumption. Mesh, being the most popular NoC …

We present a tool-supported approach to the validation of system-level timing properties in
formal models of distributed real-time embedded systems. Our aim is to provide system …