A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A 20-GHz PLL with 20.9-fs random jitter
Y Zhao, M Forghani, B Razavi - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
This article describes an integer-phase-locked loop (PLL) that incorporates a phase detector
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness
In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
A harmonic-mixing PLL architecture for millimeter-wave application
A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by
the invariably large closed-loop gain and the high operation frequency of the voltage …
the invariably large closed-loop gain and the high operation frequency of the voltage …
A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N
This letter proposes a mm-wave fractional-N reference-oversampling (ROS) all-digital phase-
locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard …
locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard …
A 480-multiplication-factor 13.2-to-17.3 GHz sub-sampling PLL achieving 6.6 mW power and-248.1 dB FoM using a proportionally divided charge pump
L Zhang, A Niknejad - 2022 IEEE International Solid-State …, 2022 - ieeexplore.ieee.org
Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today's ever-
growing wireless and wireline communication systems. To meet the stringent requirements …
growing wireless and wireline communication systems. To meet the stringent requirements …
Flicker phase-noise reduction using gate–drain phase shift in transformer-based oscillators
This article presents a wide-band suppression technique of flicker phase noise (PN) by
means of a gate–drain phase shift in a transformer-based complementary oscillator. We …
means of a gate–drain phase shift in a transformer-based complementary oscillator. We …
A 27-39 GHz Fractional-N PLL For 5G mm-Wave Communication With Improved Extended Range Multi-Modulus Divider
K Sun, L Lu, S Ye, J Wang, L Li… - 2023 Asia-Pacific …, 2023 - ieeexplore.ieee.org
This paper presents a 27-39 GHz fractional-N PLL (FN-PLL) with its phase noise analysis,
optimization and design for the future fifth generation (5G) millimeter wave wireless …
optimization and design for the future fifth generation (5G) millimeter wave wireless …
Digitally Intensive RF/Millimetre-Wave Frequency Generation Techniques
X Chen - 2022 - researchrepository.ucd.ie
The advanced wireless communication standards (eg, 5G) placed stringent specifications on
the RF/mm-wave transceivers. As a main contributor to the total error vector magnitude …
the RF/mm-wave transceivers. As a main contributor to the total error vector magnitude …
[图书][B] Low Jitter Techniques for High-Speed Phase-Locked Loops
Y Zhao - 2022 - search.proquest.com
The problem of clock generation with low jitter becomes much more challenging as wireline
transceivers are designed for higher data rates, eg, 224 Gb/s. This dissertation addresses …
transceivers are designed for higher data rates, eg, 224 Gb/s. This dissertation addresses …