HREN: A hybrid reliable and energy-efficient network-on-chip architecture
P Bhamidipati, A Karanth - IEEE Transactions on Emerging …, 2022 - ieeexplore.ieee.org
As transistor scales down to sub-nanometer and processing cores with billions of transistors
are integrated, reliable and energy-efficient Network-on-Chip (NoC) architectures are critical …
are integrated, reliable and energy-efficient Network-on-Chip (NoC) architectures are critical …
A survey on network on chip routing algorithms criteria
As number of components on the semi-conductor industry is growing at a healthy rate,
results in an increase in number of cores integrating on a chip.. Demand for core …
results in an increase in number of cores integrating on a chip.. Demand for core …
Optimal soft error mitigation in wireless communication using approximate logic circuits
The development of in chip manufacturing processes has enhanced energy-efficient nano-
electronic and high-performance devices in daily activities. In recent times, CMOS …
electronic and high-performance devices in daily activities. In recent times, CMOS …
Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip
B Bhowmik - Microelectronics Reliability, 2023 - Elsevier
The guaranteed delivery of application packets from source to destination in a network-on-
chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a …
chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a …
Improving reliability in spidergon network on chip-microprocessors
Aggressive technology scaling continues to make networks-on-chip (NoCs) vulnerable to
failures that relentlessly result in reliability concerns and unexpected system performance …
failures that relentlessly result in reliability concerns and unexpected system performance …
Locating open-channels in octagon networks on chip-microprocessors
Networks-on-chip (NoCs) provide the essential communication infrastructure for building
today's on-chip multiprocessors. Albeit mesh is commonly used as the underlying …
today's on-chip multiprocessors. Albeit mesh is commonly used as the underlying …
Quad-rail sense-amplifier based NoC router design
N Ashokkumar, P Nagarajan, N Vithyalakshmi… - … on Intelligent Data …, 2019 - Springer
Sense-amplifier half-buffer method with quad-rail (ie, 1-of-4) data programming is focus
about power and Low area Overhead in Low Power applications in asynchronous logic …
about power and Low area Overhead in Low Power applications in asynchronous logic …
Hardware Security in Emerging Photonic Network-on-Chip Architectures
IG Thakkar, SVR Chittamuru, V Bhat… - … : From Devices to …, 2022 - Springer
Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using
photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal …
photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal …
System management recovery protocol for MPSoCs
The advances in silicon technology lead to systems with hundreds of processors, the NoC-
based MPSoCs. However, the higher fault probability in deep sub-micron technologies …
based MPSoCs. However, the higher fault probability in deep sub-micron technologies …
Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip
In the presence of deep submicron noise, providing reliable and energy‐efficient network on‐
chip operation is becoming a challenging objective. In this study, the authors propose a …
chip operation is becoming a challenging objective. In this study, the authors propose a …