Performance evaluation of application mapping approaches for network-on-chip designs

W Amin, F Hussain, S Anjum, S Khan, NK Baloch… - IEEE …, 2020 - ieeexplore.ieee.org
Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of
cores on a single system-on-chip (SoC). The dependency on multi-core systems to …

The CTH Network: An NoC Platform for Scalable and Energy Efficient Application Mapping Solution

A Bose, P Ghosal - IEEE Transactions on Nanotechnology, 2023 - ieeexplore.ieee.org
Multi-threaded design of the applications has given a new dimension to the execution
concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication …

Visualnoc: A visualization and evaluation environment for simulation and mapping

J Wang, Y Huang, M Ebrahimi, L Huang, Q Li… - Proceedings of the …, 2016 - dl.acm.org
Simulation is the most common approach to evaluate Network on Chip (NoC) designs and
many simulators at different abstraction levels have been developed so far. However …

A lifetime-aware mapping algorithm to extend MTTF of networks-on-chip

L Huang, S Chen, Q Wu, M Ebrahimi… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
Fast aging of components has become one of the major concerns in Systems-on-Chip with
further scaling of the submicron technology. This problem accelerates when combined with …

Optimizing dynamic mapping techniques for on-line NoC test

S Jiang, Q Wu, S Chen, J Wang… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
With the aggressive scaling of submicron technology, intermittent faults are becoming one of
the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test …

Testing aware dynamic mapping for path-centric network-on-chip test

S Jiang, Q Wu, S Chen, J Zhan, J Wang, M Ebrahimi… - Integration, 2019 - Elsevier
With the aggressive scaling of submicron technology, intermittent faults are becoming one of
the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test …

Scalable Run-time Task Mapping on BNoC Topology Focusing on Energy-efficiency

A Bose, P Ghosal - … 15th IEEE/ACM International Workshop on …, 2022 - ieeexplore.ieee.org
The current work demonstrates a run-time application mapping technique on the BNoC
network. Crucial properties of the BNoC design like low diameter and high path diversity …

Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system

L Wang, S Jiang, S Chen, J Wang, L Huang - Integration, 2019 - Elsevier
Fast aging of components has become one of the major concerns in Systems-on-Chip with
further scaling of the submicron technology, which is accelerated when the working …

Towards Efficient Reuse of Software Programmable Streaming Coarse Grained Reconfigurable Architectures

EB Franco - 2021 - theses.hal.science
Coarse-Grained Reconfigurable Architectures (CGRA) are designed to deliver high
performance while drastically reducing the latency of the computing system. There are …

Research on robust design and optimization of embedded network electronic information system

P Yang, X Zhou, J Jia - Journal of Physics: Conference Series, 2020 - iopscience.iop.org
At present, in the process of designing and optimizing the robustness of embedded network
electronic information systems, it is found that many factors in the system have some …