As clock skew and power consumption become major challenges in deep submicron design
of synchronous circuits, asynchronous designs, especially Null Convention Logic (NCL) …

Quasi delay-insensitive design is a promising solution for coping with contemporary silicon
technology problems such as aggressive process variations and tight power budgets …

NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power
robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for …

This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the
use of this tool in the production of a cell library for asynchronous logic components called …

Asynchronous paradigms are a way to deal with hard problems in newer technologies.
Among the templates for ensuring efficient asynchronous design, Null Convention Logic …

NULL convention logic (NCL) is a promising design paradigm for constructing asynchronous
delay-insensitive circuits. This brief presents two novel NCL pipeline structures, called fine …

For decades now, the synchronous paradigm has been the major choice of the industry for
building integrated circuits. Unfortunately, with the development of semiconductor industry …

This work presents the ASCEnD flow, a design flow devised for the design of components
required for the design of asynchronous systems using standard-cells. The flow is fully …

This work scrutinizes the implementation and performance analysis of novel self-timed
asynchronous logic. These templates are based on a delay-insensitive (DI) logic paradigm …

This brief proposes a new topology for implementing differential null convention logic gates.
The new topology relies on the static implementation of conventional versions of such gates …