the invention relates to an architecture for a scan-based integrated circuit (IC). More
specifically, the invention relates to a method and circuitry to reduce cycle time in shifting …

Roughly described, a scan-based test architecture is optimized in dependence upon the
circuit design under consideration. In one embodiment, a plurality of candidate test designs …

(57) ABSTRACT A scan-based circuit includes a selector that is implemented by multiple
observation logics. Each observation logic is coupled to a scan chain to receive data to be …

Three-dimensional processing systems are provided which have multiple layers of
conjoined chips, wherein at least one chip layer has calibration control circuitry that is …

A test architecture adds minimal area overhead and increases encoding bandwidth by using
one or more cyclical cache chains for a set of the test patterns provided to the scan chains of …

(57) ABSTRACT A scan-testable integrated circuit includes first and second flip-flops. The
first flip-flop includes first and second latches and the second flip-flop includes third and …

The present invention relates to test architectures for inte grated circuits, and in particular to
test architectures that allows changing values on the scan configuration signals during the …

A scan chain partition includes a serial input coupled to a scan input signal pin of a module
under test. A plurality of scan sub-chains is coupled to the serial input. A scan sub-chain …

A semiconductor integrated circuit equipped with multiple serially coupled scan chains
which are used to shift inspection data based on different clock signals in order to inspect a …

A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This
test architecture advantageously allows for changing scan inputs during the scan operation …