Current studies and applications of shuffled frog leaping algorithm: a review
Abstract Shuffled Frog Leaping Algorithm (SFLA) is one of the most widespread algorithms.
It was developed by Eusuff and Lansey in 2006. SFLA is a population-based metaheuristic …
It was developed by Eusuff and Lansey in 2006. SFLA is a population-based metaheuristic …
Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey
Abstract Network on Chip (NoC) is an interesting technology that benefits from several
processing elements and the necessary communication facilities, to provide an answer to …
processing elements and the necessary communication facilities, to provide an answer to …
AI-optimized cost-aware design strategies for resource-efficient applications
RSSK Dittakavi - Journal of Science & Technology, 2023 - thesciencebrigade.com
In the context of modern computing landscapes marked by escalating resource demands
and cost considerations, this paper introduces a novel framework that integrates artificial …
and cost considerations, this paper introduces a novel framework that integrates artificial …
Efficient application mapping approach based on grey wolf optimization for network on chip
In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a
critical solution, offering scalability, flexibility, modularity, and efficiency. However, a …
critical solution, offering scalability, flexibility, modularity, and efficiency. However, a …
Heuristic algorithm for task mapping problem in a hierarchical wireless network-on-chip architecture
M Sacanamboy - Cluster Computing, 2024 - Springer
Given the complexity and wide range of applications being developed for the Internet of
Things (IoT) requiring an efficient mapping of application tasks in hardware resources …
Things (IoT) requiring an efficient mapping of application tasks in hardware resources …
Multiobjective piecewise regressive elitism spotted hyena optimized mapping for 3D NoC architecture design
L Gopalakrishnan, SB Ko - International Journal of Information …, 2023 - Springer
Abstract Networks-on-chip (NoC) has network-based communication among operating
cores and intellectual property (IP) cores combined on a similar chip. Existing NoC designs …
cores and intellectual property (IP) cores combined on a similar chip. Existing NoC designs …
FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC
E Khodadadi, B Barekatain, E Yaghoubi… - The Journal of …, 2022 - Springer
In recent years, using three-dimensional Network-on-Chip (3D-NoC) has increased due to
its high performance and integration of processing elements. However, as technology …
its high performance and integration of processing elements. However, as technology …
NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors
NB Renani, E Yaghoubi, N Sadehnezhad… - The Journal of …, 2022 - Springer
Regarding the increase in the number of cores in the electronic network-on-chip, they may
not be an ideal choice in the response of needing latency, power, and reliability. However …
not be an ideal choice in the response of needing latency, power, and reliability. However …
SpecMap: An efficient spectral partitioning based static application mapping algorithm for 2D mesh NoCs
RSR Raj, A Joseph, S Kalady - Concurrency and Computation …, 2023 - Wiley Online Library
Summary Network‐on‐chip (NoC) is adopted as a flexible and effective communication
backbone by multiprocessor systems with core counts ranging from a few to hundreds. The …
backbone by multiprocessor systems with core counts ranging from a few to hundreds. The …
HDSAP: heterogeneity-aware dynamic scheduling algorithm to improve performance of nanoscale many-core processors for unknown workloads
K Kia, A Rajabzadeh - The Journal of Supercomputing, 2023 - Springer
The performance growth in processors has been continuing toward increasing the number
of processing cores on the chip and scaling the feature size of transistors. However, in the …
of processing cores on the chip and scaling the feature size of transistors. However, in the …