Analysis, transformation and optimization for high perfomance parallel computing

AА Prihozhy - 2019 - rep.bntu.by
This book studies hardware and software specifications at algorithmic level from the point of
measuring and extracting the potential parallelism hidden in them. It investigates the …

Design productivity of a high level synthesis compiler versus HDL

M Pelcat, C Bourrasset, L Maggiani… - … on embedded computer …, 2016 - ieeexplore.ieee.org
The complexity of hardware systems is currently growing faster than the productivity of
system designers and programmers. This phenomenon is called Design Productivity Gap …

Spider: A synchronous parameterized and interfaced dataflow-based rtos for multicore dsps

J Heulot, M Pelcat, K Desnos… - 2014 6th European …, 2014 - ieeexplore.ieee.org
This paper introduces a novel Real-Time Operating System (RTOS) based on a
parameterized dataflow Model of Computation (MoC). This RTOS, called Synchronous …

CAPH: a language for implementing stream-processing applications on FPGAs

J Sérot, F Berry, S Ahmed - Embedded Systems Design with FPGAs, 2013 - Springer
We introduce CAPH, a new domain-specific language (DSL) suited to the implementation of
stream-processing applications on field programmable gate arrays (FPGA). CAPH relies …

FLOWER: A comprehensive dataflow compiler for high-level synthesis

P Amiri, A Pérard-Gayot, R Membarth… - … Conference on Field …, 2021 - ieeexplore.ieee.org
FPGAs have found their way into data centers as accelerator cards, making reconfigurable
computing more accessible for high-performance applications. At the same time, new high …

Built-in self-testing of micropipelines

OA Petlin, SB Furber - Proceedings Third International …, 1997 - ieeexplore.ieee.org
An asynchronous ARM6 microprocessor (AMULET1), designed at the University of
Manchester using a two-phase signalling protocol, and the latest release of the AMULET2e …

Realizing efficient execution of dataflow actors on manycores

E Gebrewahid, M Yang, G Cedersjö… - 2014 12th IEEE …, 2014 - ieeexplore.ieee.org
Embedded DSP computing is currently shifting towards manycore architectures in order to
cope with the ever growing computational demands. Actor based dataflow languages are …

Implementing stream-processing applications on fpgas: A dsl-based approach

J Serot, F Berry, S Ahmed - 2011 21st International Conference …, 2011 - ieeexplore.ieee.org
We introduce CAPH, a new domain-specific language (DSL) suited to the implementation of
stream-processing applications on field programmable gate arrays (FPGA). CAPH relies …

High-level dataflow programming for reconfigurable computing

J Sérot, F Berry - 2014 International Symposium on Computer …, 2014 - ieeexplore.ieee.org
In many application domains, FPGAs are now promoted as a way of getting round the
restrictions of specific CPU designs on system scalability. However, in the current state-of …

High-level dataflow programming for real-time image processing on smart cameras

J Sérot, F Berry, C Bourrasset - Journal of Real-Time Image Processing, 2016 - Springer
We describe the application of the caph programming language to the implementation of
complex real-time image processing application on a FPGA embedded in a smart camera …