A low-power comparator is presented. pMOS transistors are used at the input of the
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the
voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in …

A new structure single‐stage dynamic comparator with a large input common‐mode range is
proposed. The proposed comparator is compared with previous dynamic comparators. With …

This paper introduces a multi-step switching scheme for a digital low dropout regulator
(DLDO) that emerges as a new way of achieving nanosecond-transient and fine-grained on …

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator.
The advantages of the proposed circuit are low kickback noise and offset. Moreover, low …

A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling interchip wireless communication interface for a
3D-stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET …

This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-
comparator for medium to high resolution Analog to Digital Converters (ADCs). The …

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS
transistors are used at the input of the first and second stages of the comparator. At the …

A structure of a dynamic comparator with high‐speed low‐power and a low‐power supply
voltage is proposed. The proposed comparator is compared with previous dynamic …

This brief presents a three-stage comparator and its modified version to improve the speed
and reduce the kickback noise. Compared to the traditional two-stage comparators, the three …