A review on performance comparison of advanced MOSFET structures below 45 nm technology node
N Mendiratta, SL Tripathi - Journal of Semiconductors, 2020 - iopscience.iop.org
CMOS technology is one of the most frequently used technologies in the semiconductor
industry as it can be successfully integrated with ICs. Every two years the number of MOS …
industry as it can be successfully integrated with ICs. Every two years the number of MOS …
18nm n-channel and p-channel Dopingless asymmetrical Junctionless DG-MOSFET: low power CMOS based digital and memory applications
N Mendiratta, SL Tripathi - Silicon, 2022 - Springer
In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG)
MOSFET has been designed for suppressed short channel effects (SCEs) for low power …
MOSFET has been designed for suppressed short channel effects (SCEs) for low power …
Design insights into thermal performance of vertically stacked JL-NSFET with high-k gate dielectric for sub 5-nm technology node
Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate
Dielectric for Sub 5-nm Technology Node - IOPscience Skip to content IOP Science home …
Dielectric for Sub 5-nm Technology Node - IOPscience Skip to content IOP Science home …
Management of night-time urinary incontinence in residential settings for older people: an investigation into the effects of different pad changing regimes on skin health …
M Fader, S Clarke-O'Neill, D Cook… - Journal of Clinical …, 2003 - search.ebscohost.com
Absorbent pads are the main method of managing urinary incontinence in residential
settings for older people. Improvements in technology have resulted in highly absorbent …
settings for older people. Improvements in technology have resulted in highly absorbent …
Surface sediment bulk geochemistry and grain-size composition related to the oceanic circulation along the South American continental margin in the Southwest …
M Frenz, R Höppner, JBW Stuut, T Wagner… - The South Atlantic in the …, 2004 - Springer
Surface sediments from the South American continental margin surrounding the Argentine
Basin were studied with respect to bulk geochemistry (CaCO 3 and C org) and grain-size …
Basin were studied with respect to bulk geochemistry (CaCO 3 and C org) and grain-size …
Fatigue characterization of a polymer foam to use as a cancellous bone analog material in the assessment of orthopaedic devices
V Palissery, M Taylor, M Browne - Journal of Materials Science: Materials …, 2004 - Springer
Analog materials are used as a substitute to cancellous bone for in vitro biomechanical tests
due to their uniformity, consistency in properties and availability. To date, only the static …
due to their uniformity, consistency in properties and availability. To date, only the static …
Solid particle erosion of diamond coatings under non-normal impact angles
DW Wheeler, RJK Wood - Wear, 2001 - Elsevier
This paper describes an erosion study, which examines the effect of impact angle on the
erosion behaviour of diamond coatings deposited on tungsten substrates by chemical …
erosion behaviour of diamond coatings deposited on tungsten substrates by chemical …
Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface
J Moers - Applied Physics A, 2007 - Springer
Tremendous progress in information technology has been made possible by the
development and optimization of metal oxide semiconductor field effect transistor (MOSFET) …
development and optimization of metal oxide semiconductor field effect transistor (MOSFET) …
Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs
E Gili, T Uchino, MMA Hakim… - IEEE electron device …, 2006 - ieeexplore.ieee.org
A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-
nm vertical MOSFETs is described. The key feature of this process is the creation of a …
nm vertical MOSFETs is described. The key feature of this process is the creation of a …
Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance
E Gili, VD Kunz, T Uchino, MMA Hakim… - IEEE transactions on …, 2006 - ieeexplore.ieee.org
Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at
the source and drain, but have very different gate overlaps and geometric configurations …
the source and drain, but have very different gate overlaps and geometric configurations …