Programmable Transistor Array Design Methodology

OMK Law, KH Wu - US Patent App. 12/616,985, 2010 - Google Patents
A method of designing integrated circuits includes providing a first chip and a second chip
identical to each other. Each of the first chip and the second chip includes a base layer …

System and method for testing and configuration of an FPGA

L Rouge, J Eydoux, M Giuffre - US Patent 10,295,595, 2019 - Google Patents
Configuration values for Lookup tables (LUTs) and programmable routing switches in an
FPGA are provided by means of a number of flip flops arranges in a shift register. This shift …

Integrated database indexing system

R Cox, B Kurtz, J Ross - US Patent App. 10/871,858, 2004 - Google Patents
An integrated database indexing system includes a database containing data and a query
source communicably connected to the database. A query router connected to the query …

Flexible sized die for use in multi-die integrated circuit

RC Camarota - US Patent 9,026,872, 2015 - Google Patents
An integrated circuit (IC) structure can include a first die and a second die. The second die
can include a first base unit and a second base unit. Each of the first base unit and the …

Programmable logic device suitable for implementation in molecular electronics

SM Trimberger - US Patent 7,187,201, 2007 - Google Patents
Pullup and pulldown structures can be formed using nanoscale programmable junctions.
These devices can be integrated into nanoscale circuit designs and can be programmably …

Increased usable programmable device dice

Y Fan, EJ Thorne, XY Li, G O'rourke… - US Patent …, 2016 - Google Patents
6,157.213 A 12/2000 Voogel generating a plurality of configuration bitstreams to imple 6,
160,418 A 12/2000 Burnham ment a circuit in the programmable device; selecting one of …

Application-specific testing methods for programmable logic devices

RW Wells, ZM Ling, RD Patrie, VL Tong, J Cho… - US Patent …, 2005 - Google Patents
Disclosed are methods for utilizing programmable logic devices that contain at least one
localized defect. Such devices are tested to determine their suitability for implementing …

System, method, and product for nanoscale modeling, analysis, simulation, and synthesis (NMASS)

R McCarthy - US Patent App. 10/248,092, 2003 - Google Patents
(57) ABSTRACT A computer-based System is described that provides users with the ability
to develop high-fidelity digital quantitative representations of physical and chemical …

Application-specific testing methods for programmable logic devices

RW Wells, ZM Ling, RD Patrie, VL Tong, J Cho… - US Patent …, 2004 - Google Patents
US6817006B1 - Application-specific testing methods for programmable logic devices - Google
Patents US6817006B1 - Application-specific testing methods for programmable logic devices …

Memory embedded semiconductor integrated circuit and a method for designing the same

T Kobayashi, N Ikeda - US Patent 6,536,013, 2003 - Google Patents
The present invention clarifies the conditions for the required element techniques to be
technically Superior and makes it easy to establish the development guideline during the …