Power device integration on a common substrate

J Korec - US Patent 8,847,310, 2014 - Google Patents
902 and body regions on at least a portion of the buried well. A shielding structure is formed
proximate the upper Surface of the active region, overlapping a gate. During conduction, the …

Power device integration on a common substrate

J Korec, B Yang - US Patent 8,674,440, 2014 - Google Patents
(57) ABSTRACT A semiconductor structure for facilitating an integration of power devices on
a common Substrate includes a first insu lating layer formed on the substrate and an active …

Power device integration on a common substrate

J Korec - US Patent 8,994,105, 2015 - Google Patents
US8994105B2 - Power device integration on a common substrate - Google Patents
US8994105B2 - Power device integration on a common substrate - Google Patents Power …

A novel high-performance trench lateral double-diffused MOSFET with buried oxide bump layer

H Jia, Y Shen, H Wang, X Wang, Y Zhang, S Zhu… - Microelectronics …, 2023 - Elsevier
A shallow-trenched Lateral Double-Diffused MOSFET with folded drift region (FD LDMOS) is
proposed in this paper. The new structure divides the drift region into two parts. The left side …

Evaluation of a “Field Cage” for electric field control in GaN-based HEMTs that extends the scalability of breakdown into the kV regime

BD Tierney, S Choi, S DasGupta… - … on Electron Devices, 2017 - ieeexplore.ieee.org
A distributed impedance “field cage” structure is proposed and evaluated for electric field
control in GaN-based, lateral high electron mobility transistors operating as kilovolt-range …

Power device integration on a common substrate

J Korec, B Yang - US Patent 8,928,116, 2015 - Google Patents
A semiconductor structure for facilitating an integration of power devices on a common
Substrate includes a first insu lating layer formed on the Substrate and an active region …

Power device integration on a common substrate

J Korec, B Yang - US Patent 9,412,881, 2016 - Google Patents
(57) A semiconductor structure for facilitating an integration of power devices on a common
substrate includes a first insu lating layer formed on the Substrate and an active region …

Power device integration on a common substrate

J Korec, B Yang - US Patent 8,994,115, 2015 - Google Patents
(57) ABSTRACT A semiconductor structure for facilitating an integration of power devices on
a common substrate includes a first insu lating layer formed on the Substrate and an active …

High-Voltage Drain-Extended FinFET With a High- Dielectric Field Plate

H Kim, H Cho, BD Kong, K Park, I Kim… - … on Electron Devices, 2020 - ieeexplore.ieee.org
A drain-extended (De) FinFET (DeFinFET) with a high-k dielectric field plate is proposed for
high-voltage (HV) system-on-chip (SoC) applications at 10-nm CMOS technology nodes …

Design of drain-extended MOS devices using RESURF techniques for high switching performance and avalanche reliability

S Pali, A Gupta - IEEE Access, 2021 - ieeexplore.ieee.org
The drift region of conventional drain extended NMOS (DeNMOS_C) is engineered to
reduce gate charge for high performance and to enhance avalanche ruggedness for …