An overview of hardware security and trust: Threats, countermeasures, and design tools

W Hu, CH Chang, A Sengupta, S Bhunia… - … on Computer-Aided …, 2020 - ieeexplore.ieee.org
Hardware security and trust have become a pressing issue during the last two decades due
to the globalization of the semiconductor supply chain and ubiquitous network connection of …

A robust FSM watermarking scheme for IP protection of sequential circuit design

A Cui, CH Chang, S Tahar… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
Finite state machines (FSMs) are the backbone of sequential circuit design. In this paper, a
new FSM watermarking scheme is proposed by making the authorship information a non …

Rethinking watermark: Providing proof of IP ownership in modern socs

NN Anandakumar, MS Rahman… - Cryptology ePrint …, 2022 - eprint.iacr.org
Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs).
Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses …

A cellular automata guided finite-state-machine watermarking strategy for IP protection of sequential circuits

R Karmakar, SS Jana… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Preventing the illegal use of Intellectual Property (IP) cores has been one of the most
fundamental challenges for the semiconductor industry. Hardware watermarking is a viable …

SoC: a real platform for IP reuse, IP infringement, and IP protection

D Saha, S Sur-Kolay - VLSI Design, 2011 - Wiley Online Library
Increased design complexity, shrinking design cycle, and low cost—this three‐dimensional
demand mandates advent of system‐on‐chip (SoC) methodology in semiconductor industry …

PSC-watermark: power side channel based IP watermarking using clock gates

U Das, MS Rahman, NN Anandakumar… - 2023 IEEE European …, 2023 - ieeexplore.ieee.org
With the ever-increasing re-use of intellectual property (IP) cores in modern system-on-chips
(SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that …

Ultra-low overhead dynamic watermarking on scan design for hard IP protection

A Cui, G Qu, Y Zhang - IEEE Transactions on Information …, 2015 - ieeexplore.ieee.org
Unlike conventional legal means, digital watermark enables an effective self-protection
mechanism for Very Large Scale Integration (VLSI) designers to protect their intellectual …

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores

M Rathor, A Anshul, K Bharath, R Chaurasia… - Computers and …, 2023 - Elsevier
Reusable hardware intellectual property (IP) cores play a significant role in the modern
system on chip (SoC) designs. However, raging threats of IP piracy and IP ownership …

A blind dynamic fingerprinting technique for sequential circuit intellectual property protection

CH Chang, L Zhang - … on Computer-Aided Design of Integrated …, 2013 - ieeexplore.ieee.org
Design fingerprinting is a means to trace the illegally redistributed intellectual property (IP)
by creating a unique IP instance with a different signature for each user. Existing …

CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme

MMM Rahman, MS Rahman, R Kibria… - 2023 IEEE 41st VLSI …, 2023 - ieeexplore.ieee.org
The ever-increasing propensity for intellectual property (IP) reuse has reduced the design
productivity gap in the supply chain. As a consequence, protecting IPs has become more …