Oscillator flicker phase noise: A tutorial

Y Hu, T Siriburanon… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in
supporting ultra-low PN frequency generation for the advanced communications and other …

Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial

Y Hu, T Siriburanon… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this tutorial brief, we introduce a unified wideband phase-noise theory framework of
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …

A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness

X Chen, Y Hu, T Siriburanon, J Du… - Ieee Journal of Solid …, 2023 - ieeexplore.ieee.org
In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …

A charge-sharing locking technique with a general phase noise theory of injection locking

Y Hu, X Chen, T Siriburanon, J Du… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …

Analysis and design of a 15.2-to-18.2-GHz inverse-class-F VCO with a balanced dual-core topology suppressing the flicker noise upconversion

X Meng, H Li, P Chen, J Yin, PI Mak… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This paper presents the theory and implementation of a balanced dual-core inverse-class-F
(class-F) voltage-controlled oscillator (VCO). The class-F topology supports high-quality …

Flicker phase-noise reduction using gate–drain phase shift in transformer-based oscillators

X Chen, Y Hu, T Siriburanon, J Du… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This article presents a wide-band suppression technique of flicker phase noise (PN) by
means of a gate–drain phase shift in a transformer-based complementary oscillator. We …

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

Y Hu, W Tao, RB Staszewski - IEEE Open Journal of the Solid …, 2024 - ieeexplore.ieee.org
A fractional-N frequency synthesizer with low total jitter eg,< 50 fsrms, accounting for both
phase noise (PN) and spurs is essential for enabling the emerging 5G/6G and other high …

An ultra‐low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications

M Bagheri, X Li - International Journal of Circuit Theory and …, 2022 - Wiley Online Library
This paper presents a fully integrated analog phase‐locked loop (PLL) fractional‐N
frequency synthesizer for 5G wireless communication and Internet‐of‐Everything (IoE) …

Advanced Frequency Synthesis Techniques Using All-Digital Phase-Locked Loops

T Siriburanon, Y Hu, J Du, RB Staszewski - Imaging Sensors, Power …, 2024 - Springer
Over the past two decades, all-digital techniques for RF frequency synthesis have gained
significant interest. In this chapter, we will review the all-digital phase-locked loop (ADPLL) …

Digitally Intensive RF/Millimetre-Wave Frequency Generation Techniques

X Chen - 2022 - researchrepository.ucd.ie
The advanced wireless communication standards (eg, 5G) placed stringent specifications on
the RF/mm-wave transceivers. As a main contributor to the total error vector magnitude …