The physics of optical computing
PL McMahon - Nature Reviews Physics, 2023 - nature.com
There has been a resurgence of interest in optical computing since the early 2010s, both in
academia and in industry, with much of the excitement centred around special-purpose …
academia and in industry, with much of the excitement centred around special-purpose …
A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI
JA Tierno, AV Rylyakov… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully
programmable proportional-integral-differential (PID) loop filter and features a third order …
programmable proportional-integral-differential (PID) loop filter and features a third order …
A 56–65 GHz injection-locked frequency tripler with quadrature outputs in 90-nm CMOS
WL Chan, JR Long - IEEE Journal of Solid-State Circuits, 2008 - ieeexplore.ieee.org
A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz
quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a …
quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a …
Linearized analysis of a digital bang-bang PLL and its validity limits applied to jitter transfer and jitter generation
N Da Dalt - IEEE Transactions on Circuits and Systems I …, 2008 - ieeexplore.ieee.org
In the last few years, several digital implementations of phase-locked loops (PLLs) have
emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang …
emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang …
Design and analysis of low-power high-frequency robust sub-harmonic injection-locked clock multipliers
A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital
frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the …
frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the …
Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank
A 60 GHz voltage-controlled oscillator with an inductive division LC tank has been designed
in 90 nm CMOS. The analysis of the oscillator shows that the presence of higher harmonics …
in 90 nm CMOS. The analysis of the oscillator shows that the presence of higher harmonics …
A 22 to 26.5 Gb/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process
This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data
recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical …
recovery (AD-CDR) fabricated in a 65 nm CMOS process. The receiver consists of an optical …
A 0.65-to-1.4 nJ/burst 3-to-10 GHz UWB all-digital TX in 90 nm CMOS for IEEE 802.15. 4a
J Ryckaert, G Van der Plas, V De Heyn… - IEEE Journal of Solid …, 2007 - ieeexplore.ieee.org
We propose an all-digital UWB transmitter architecture that exploits the low duty cycle of
impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE …
impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE …
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in …
Sub-harmonically injection locked oscillators provide a simple means for generating very-
low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free …
low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free …
Design of on-chip readout circuitry for spin-wave devices
We present the design of readout circuitry based on complementary metal-oxide
semiconductors (CMOS) for spin-waves. The circuit provides the functionality of a high …
semiconductors (CMOS) for spin-waves. The circuit provides the functionality of a high …