NBTI-generated defects in nanoscaled devices: Fast characterization methodology and modeling

R Gao, Z Ji, AB Manut, JF Zhang… - … on Electron Devices, 2017 - ieeexplore.ieee.org
Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely
observed and known to play an important role in device's lifetime. However, its …

Key issues and solutions for characterizing hot carrier aging of nanometer scale nMOSFETs

M Duan, JF Zhang, Z Ji, WD Zhang… - … on Electron Devices, 2017 - ieeexplore.ieee.org
Silicon bandgap limits the reduction of operation voltage when downscaling device sizes.
This increases the electrical field within-a-device and hot carrier aging (HCA) is becoming …

Investigation of negative bias temperature instability effect in partially depleted SOI pMOSFET

C Peng, Z Lei, R Gao, Z Zhang, Y Chen, Y En… - IEEE …, 2020 - ieeexplore.ieee.org
The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O)
devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are …

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

C Peng, Y En, Z Lei, R Gao, Z Zhang… - … on Nuclear Science, 2021 - ieeexplore.ieee.org
The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect
of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened …

[图书][B] Bias Temperature Instability Modelling and Lifetime Prediction on Nano-scale MOSFETs

R Gao - 2018 - search.proquest.com
Abstract Bias Temperature Instability (BTI) is one of the most important reliability concerns
for Metal Oxide Semiconductor Field Effect Transistors (MOSFET), the basic unit in …

Research on negative bias temperature instability effects under the coupling of total ionizing dose irradiation for PDSOI MOSFETs

C Peng, R Gao, Z Lei, Z Zhang, Y Chen, YF En… - IEEE …, 2021 - ieeexplore.ieee.org
The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on
insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and …

Voltage step stress: a technique for reducing test time of device ageing

JF Zhang, Z Ji, M Duan, W Zhang… - … Conference on IC …, 2019 - ieeexplore.ieee.org
Device ageing leads to circuit malfunction and must be controlled. During ageing, defects
build up slowly and the test is time consuming and costly. The typical ageing tests are …

Bias and Temperature Stress Effects in IGZO TFTs and the Application of Step-Stress Testing to Increase Reliability Test Throughput

N Mohammadian, D Kumar, L Fugikawa-Santos… - Authorea …, 2023 - techrxiv.org
Indium-gallium-zinc-oxide thin-film transistors (IGZO TFTs) are widely used in numerous
display applications and are emerging as a promising alternative for flexible IC production …

Overshoot Stress on Ultra-Thin HfO2 High- Layer and Its Impact on Lifetime Extraction

G Wan, T Duan, S Zhang, L Jiang… - IEEE Electron …, 2015 - ieeexplore.ieee.org
Overshoot stress (stimulating the actual IC operating condition) on an ultra-thin HfO2 (EOT~
0.8 nm) high-κ layer is investigated, which reveals that overshoot is of great importance to …

[图书][B] Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

AB Manut - 2020 - search.proquest.com
One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate
dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA) …