Taguchi approach and response surface analysis for design of a high-performance single-walled carbon nanotube bundle interconnects in a full adder

S Ghorbani, K Reaz Kashyzadeh - International Journal of Engineering, 2020 - ije.ir
In this study, it was attempted to design a high-performance single-walled carbon nanotube
(SWCNT) bundle interconnects in a full adder. For this purpose, the circuit performance was …

[HTML][HTML] Fast and energy efficient full adder circuit using 14 CNFETs

JK Saini, A Srinivasulu, R Kumawat - Solid State Electronics Letters, 2020 - Elsevier
With the increasing demand for faster, efficient and robust computational devices, the
industrial research in circuit design deals with the challenges like size, power, efficiency and …

DLPA: Discrepant low PDP 8-bit adder

M Ghadiry, M Nadi, AK A'Ain - Circuits, Systems, and Signal Processing, 2013 - Springer
This paper presents a new 8-bit adder circuit, called discrepant low PDP 8-bit adder (DLPA)
based on three new full adder cells, which have been designed based on requirements of …

A CNFET full adder cell design for high-speed arithmetic units

MM GHANAGHESTANI, B Ghavami… - Turkish Journal of …, 2017 - journals.tubitak.gov.tr
Carbon nanotube field-effect transistors (CNFETs) utilize an array of carbon nanotubes as
the channel material instead of bulk silicon in the traditional MOSFET structure, which holds …

[PDF][PDF] A low-power high-speed full adder cell using carbon nanotube field-effect transistors

RR Eamani, V Nallathambi… - Indonesian Journal of …, 2023 - academia.edu
The adder circuit is basic component of arithmetic logic design and that is the most important
block of processor architecture. Moreover, power consumption is the main concern for real …

CNTFET-based design of a high-efficient full adder using XOR logic

S Hatefinasab - Журнал нано-та електронної фізики, 2016 - irbis-nbuv.gov.ua
This paper presents a new low power and high speed full adder based on Carbon Nano
Tube Field Effect Transistor (CNTFET) technology. This proposed full adder is based on a …

A model for length of saturation velocity region in double-gate Graphene nanoribbon transistors

MH Ghadiry, MT Ahmadi, A Abd Manaf - Microelectronics Reliability, 2011 - Elsevier
Length of saturation region (LVSR) as an important parameter in nanoscale devices, which
controls the drain breakdown voltage is in our focus. This paper presents three models for …

CNFET-based design of energy-efficient symmetric three-input XOR and full adder circuits

S Mehrabi, RF Mirzaee, MH Moaiyeri, K Navi… - Arabian Journal for …, 2013 - Springer
This paper presents a novel CNFET-based design for three-input Exclusive-OR circuits as
well as Full Adder cells for low-voltage and high frequency applications. These designs take …

An analytical approach to study breakdown mechanism in graphene nanoribbon field effect transistors

M Ghadiry, M Nadi, M Saiedmanesh… - … of Computational and …, 2014 - ingentaconnect.com
A semi-analytical model for breakdown voltage (BV) of double gate GNR FET (DG-GNRFET)
is presented. Firstly, a model for ionization coefficient of GNR is presented and verified using …

An applicable high-efficient CNTFET-based full adder cell for practical environments

M Moradi, RF Mirzaee, MH Moaiyeri… - The 16th CSI …, 2012 - ieeexplore.ieee.org
Full adder is among the most practical logic blocks. It is the main arithmetical component of
all digital systems. This paper presents the novel design of a high-speed and high-efficient …