[PDF][PDF] Database architecture optimized for the new bottleneck: Memory access
In the past decade, advances in speed of commodity CPUs have far out-paced advances in
memory latency. Main-memory access is therefore increasingly a performance bottleneck for …
memory latency. Main-memory access is therefore increasingly a performance bottleneck for …
[PDF][PDF] Архитектура компьютера
Э Таненбаум - 2003 - dump.denr01.com
В основе первых трех изданий книги лежит идея о том, что компьютер можно
рассматривать как иерархию уровней, каждый из которых выполняет какую-либо …
рассматривать как иерархию уровней, каждый из которых выполняет какую-либо …
The Garp architecture and C compiler
Various projects and products have been built using off-the-shelf field-programmable gate
arrays (FPGAs) as computation accelerators for specific tasks. Such systems typically …
arrays (FPGAs) as computation accelerators for specific tasks. Such systems typically …
Optimizing main-memory join on modern hardware
In the past decade, the exponential growth in commodity CPU's speed has far outpaced
advances in memory latency. A second trend is that CPU performance advances are not …
advances in memory latency. A second trend is that CPU performance advances are not …
Optimizing database architecture for the new bottleneck: memory access
In the past decade, advances in the speed of commodity CPUs have far out-paced advances
in memory latency. Main-memory access is therefore increasingly a performance bottleneck …
in memory latency. Main-memory access is therefore increasingly a performance bottleneck …
Using the compiler to improve cache replacement decisions
Z Wang, KS McKinley, AL Rosenberg… - Proceedings …, 2002 - ieeexplore.ieee.org
Memory performance is increasingly determining microprocessor performance and
technology trends are exacerbating this problem. Most architectures use set-associative …
technology trends are exacerbating this problem. Most architectures use set-associative …
A programming system for the imagine media processor
PR Mattson - 2002 - search.proquest.com
Media processing applications motivate new processor architectures that place new
burdens on the compiler. These applications demand very high arithmetic rates and data …
burdens on the compiler. These applications demand very high arithmetic rates and data …
Microprocessor with improved data stream prefetching
KE Diefendorff - US Patent 7,177,985, 2007 - Google Patents
(57) ABSTRACT A microprocessor With multiple stream prefetch engines each executing a
stream prefetch instruction to prefetch a complex data stream speci? ed by the instruction in …
stream prefetch instruction to prefetch a complex data stream speci? ed by the instruction in …
[图书][B] Augmenting a microprocessor with reconfigurable hardware
JR Hauser - 2000 - search.proquest.com
As VLSI technology continues to improve, configurable hardware devices such as PLDs are
progressively replacing many specialized digital integrated circuits. Field-programmable …
progressively replacing many specialized digital integrated circuits. Field-programmable …
Cooperative caching with keep-me and evict-me
JB Sartor, S Venkiteswaran… - 9th Annual Workshop …, 2005 - ieeexplore.ieee.org
Cooperative caching seeks to improve memory system performance by using compiler
locality hints to assist hardware cache decisions. In this paper, the compiler suggests cache …
locality hints to assist hardware cache decisions. In this paper, the compiler suggests cache …