[图书][B] Computer architecture: a quantitative approach
JL Hennessy, DA Patterson - 2017 - books.google.com
Computer Architecture: A Quantitative Approach, Sixth Edition has been considered
essential reading by instructors, students and practitioners of computer design for over 20 …
essential reading by instructors, students and practitioners of computer design for over 20 …
[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
[图书][B] Computer architecture
DA Patterson, FP Brooks Jr, IE Sutherland… - 2011 - wallawalla.simplesyllabus.com
Bulletin Description: Study of the organization and architecture of computer systems.
Students will understand how to measure computer performance, the basics of instruction …
Students will understand how to measure computer performance, the basics of instruction …
[图书][B] Advanced computer architecture: parallelism, scalability, programmability
Course Syllabus Course Title: Advanced Computer Architecture Page 1 Page 1 of 5
Philadelphia University Faculty of Information Technology Department of Computer Science …
Philadelphia University Faculty of Information Technology Department of Computer Science …
Instruction-level parallel processing: History, overview, and perspective
BR Rau, JA Fisher - The journal of Supercomputing, 1993 - Springer
Instruction-level parallelism (ILP) is a family of processor and compiler design techniques
that speed up execution by causing individual machine operations to execute in parallel …
that speed up execution by causing individual machine operations to execute in parallel …
Computer processor with an efficient means of executing many instructions simultaneously
MH Branigin - US Patent 5,471,593, 1995 - Google Patents
First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
23781421&utm_source= google_patent&utm_medium= platform_link&utm_campaign …
23781421&utm_source= google_patent&utm_medium= platform_link&utm_campaign …
Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
GS Sohi - IEEE transactions on computers, 1990 - ieeexplore.ieee.org
The problems of data dependency resolution and precise interrupt implementation in
pipelined processors are combined. A design for a hardware mechanism that resolves …
pipelined processors are combined. A design for a hardware mechanism that resolves …
Checkpoint repair for out-of-order execution machines
WW Hwu, YN Patt - Proceedings of the 14th annual international …, 1987 - dl.acm.org
Out-of-order execution and branch prediction are two mechanisms that can be used
profitably in the design of Supercomputers to increase performance. Unfortunately this …
profitably in the design of Supercomputers to increase performance. Unfortunately this …
Highly concurrent scalar processing
PYT Hsu, ES Davidson - ACM SIGARCH Computer Architecture News, 1986 - dl.acm.org
High speed scalar processing is an essential characteristic of high performance general
purpose computer systems. Highly concurrent execution of scalar code is difficult due to data …
purpose computer systems. Highly concurrent execution of scalar code is difficult due to data …
Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms
P Manet, B Rousseau - US Patent 9,275,002, 2016 - Google Patents
The present invention relates to a processor which comprises processing elements that
execute instructions in parallel and are connected together with point-to-point …
execute instructions in parallel and are connected together with point-to-point …