A systematic literature review on binary neural networks

R Sayed, H Azmi, H Shawkey, AH Khalil… - IEEE Access, 2023 - ieeexplore.ieee.org
This paper presents an extensive literature review on Binary Neural Network (BNN). BNN
utilizes binary weights and activation function parameters to substitute the full-precision …

Metasurface on integrated photonic platform: from mode converters to machine learning

Z Wang, Y Xiao, K Liao, T Li, H Song, H Chen… - …, 2022 - degruyter.com
Integrated photonic circuits are created as a stable and small form factor analogue of fiber-
based optical systems, from wavelength-division multiplication transceivers to more recent …

Mixed-signal computing for deep neural network inference

B Murmann - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
Modern deep neural networks (DNNs) require billions of multiply-accumulate operations per
inference. Given that these computations demand relatively low precision, it is feasible to …

Redress: Generating compressed models for edge inference using tsetlin machines

S Maheshwari, T Rahman, R Shafik… - … on Pattern Analysis …, 2023 - ieeexplore.ieee.org
Inference at-the-edge using embedded machine learning models is associated with
challenging trade-offs between resource metrics, such as energy and memory footprint, and …

T-PIM: An energy-efficient processing-in-memory accelerator for end-to-end on-device training

J Heo, J Kim, S Lim, W Han… - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
Recently, on-device training has become crucial for the success of edge intelligence.
However, frequent data movement between computing units and memory during training …

Digital versus analog artificial intelligence accelerators: Advances, trends, and emerging designs

J Seo, J Saikia, J Meng, W He, H Suh… - IEEE Solid-State …, 2022 - ieeexplore.ieee.org
For state-of-the-art artificial intelligence (AI) accelerators, there have been large advances in
both all-digital and analog/mixed-signal circuit-based designs. This article presents a …

Real-time decoding for fault-tolerant quantum computing: Progress, challenges and outlook

F Battistel, C Chamberland, K Johar… - Nano …, 2023 - iopscience.iop.org
Quantum computing is poised to solve practically useful problems which are computationally
intractable for classical supercomputers. However, the current generation of quantum …

Guarding machine learning hardware against physical side-channel attacks

A Dubey, R Cammarota, V Suresh, A Aysu - ACM Journal on Emerging …, 2022 - dl.acm.org
Machine learning (ML) models can be trade secrets due to their development cost. Hence,
they need protection against malicious forms of reverse engineering (eg, in IP piracy). With a …

Modulonet: Neural networks meet modular arithmetic for efficient hardware masking

A Dubey, A Ahmad, MA Pasha… - IACR Transactions on …, 2022 - tches.iacr.org
Intellectual Property (IP) thefts of trained machine learning (ML) models through side-
channel attacks on inference engines are becoming a major threat. Indeed, several recent …

An eight-core RISC-V processor with compute near last level cache in Intel 4 CMOS

GK Chen, PC Knag, C Tokunaga… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
An eight-core 64-b processor extends RISC-V to perform multiply–accumulate (MAC) within
the shared last level cache (LLC). Instead of moving data from the LLC to the core, compute …