A 45 nm resilient microprocessor core for dynamic variation tolerance
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to
mitigate the clock frequency (F CLK) guardbands for dynamic parameter variations to …
mitigate the clock frequency (F CLK) guardbands for dynamic parameter variations to …
Reliable on-chip systems in the nano-era: Lessons learnt and future trends
Reliability concerns due to technology scaling have been a major focus of researchers and
designers for several technology nodes. Therefore, many new techniques for enhancing and …
designers for several technology nodes. Therefore, many new techniques for enhancing and …
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
G Kornaros, D Pnevmatikatos - ACM Transactions on Design Automation …, 2013 - dl.acm.org
Billion transistor systems-on-chip increasingly require dynamic management of their
hardware components and careful coordination of the tasks that they carry out. Diverse real …
hardware components and careful coordination of the tasks that they carry out. Diverse real …
DNN engine: A 28-nm timing-error tolerant sparse deep neural network processor for IoT applications
This paper presents a 28-nm system-on-chip (SoC) for Internet of things (IoT) applications
with a programmable accelerator design that implements a powerful fully connected deep …
with a programmable accelerator design that implements a powerful fully connected deep …
A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
D Bull, S Das, K Shivashankar… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
Razor is a hybrid technique for dynamic detection and correction of timing errors. A
combination of error detecting circuits and micro-architectural recovery mechanisms creates …
combination of error detecting circuits and micro-architectural recovery mechanisms creates …
Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating
M Cho, ST Kim, C Tokunaga… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
In high volume manufacturing, conventional approach to deal with inverse-temperature
dependence (ITD) and aging is to add a post silicon flat voltage guard band to all dies based …
dependence (ITD) and aging is to add a post silicon flat voltage guard band to all dies based …
Bubble Razor: An architecture-independent approach to timing-error detection and correction
Several methods that eliminate timing margins by detecting and correcting transient delay
errors have been proposed. These Razor-style systems replace critical flip-flops with ones …
errors have been proposed. These Razor-style systems replace critical flip-flops with ones …
Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling
Parameter variations have become a dominant challenge in microprocessor design. Voltage
variation is especially daunting because it happens so rapidly. We measure and …
variation is especially daunting because it happens so rapidly. We measure and …
Robust system design to overcome CMOS reliability challenges
Today's mainstream electronic systems typically assume that transistors and interconnects
operate correctly over their useful lifetime. With enormous complexity and significantly …
operate correctly over their useful lifetime. With enormous complexity and significantly …
Time-borrowing circuit designs and hardware prototyping for timing error resilience
As dynamic variability increases with CMOS scaling, it is essential to incorporate large
design-time timing margins to ensure yield and reliable operation. Online techniques for …
design-time timing margins to ensure yield and reliable operation. Online techniques for …