[HTML][HTML] A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives
In recent years, the limits of the multicore approach emerged in the so-called “dark silicon”
issue and diminishing returns of an ever-increasing core count. Hardware manufacturers …
issue and diminishing returns of an ever-increasing core count. Hardware manufacturers …
Pushing the level of abstraction of digital system design: A survey on how to program fpgas
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …
Extending high-level synthesis for task-parallel programs
C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-
programmable gate array (FPGA) accelerators in many application domains in recent years …
programmable gate array (FPGA) accelerators in many application domains in recent years …
Taskstream: Accelerating task-parallel workloads by recovering program structure
V Dadu, T Nowatzki - Proceedings of the 27th ACM International …, 2022 - dl.acm.org
Reconfigurable accelerators, like CGRAs and dataflow architectures, have come to
prominence for addressing data-processing problems. However, they are largely limited to …
prominence for addressing data-processing problems. However, they are largely limited to …
Reconfigurable architectures: The shift from general systems to domain specific solutions
Reconfigurable computing is an expanding field that, during the last decades, has evolved
from a relatively closed community, where hard skilled developers deployed high …
from a relatively closed community, where hard skilled developers deployed high …
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
Dataflow architectures are growing in popularity due to their potential to mitigate the
challenges posed by the memory wall inherent to the Von Neumann architecture. At the …
challenges posed by the memory wall inherent to the Von Neumann architecture. At the …
Trireme: Exploration of hierarchical multi-level parallelism for hardware acceleration
The design of heterogeneous systems that include domain specific accelerators is a
challenging and time-consuming process. While taking into account area constraints …
challenging and time-consuming process. While taking into account area constraints …
ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators
S Han, M Jang, J Kang - Proceedings of the 28th ACM International …, 2023 - dl.acm.org
Functional programming's benefits for hardware description have long been recognized in
the literature. In particular, functional hardware description languages provide combinators …
the literature. In particular, functional hardware description languages provide combinators …
OpenCilk: A modular and extensible software infrastructure for fast task-parallel code
TB Schardl, ITA Lee - Proceedings of the 28th ACM SIGPLAN Annual …, 2023 - dl.acm.org
This paper presents OpenCilk, an open-source software infrastructure for task-parallel
programming that allows for substantial code reuse and easy exploration of design choices …
programming that allows for substantial code reuse and easy exploration of design choices …
使用HLS 开发FPGA 异构加速系统: 问题, 优化方法和机遇.
徐诚, 郭进阳, 李超, 王靖, 汪陶磊… - Journal of Frontiers of …, 2023 - search.ebscohost.com
目前, 现场可编程门阵列(field programmable gate array, FPGA) 由于可编程性与出色的能效比
受到了学术界与工业界的青睐, 但是传统的基于硬件描述语言的FPGA 开发方式面临编程挑战 …
受到了学术界与工业界的青睐, 但是传统的基于硬件描述语言的FPGA 开发方式面临编程挑战 …