Reconfigurable field effect transistors: A technology enablers perspective

T Mikolajick, G Galderisi, S Rai, M Simon, R Böckle… - Solid-State …, 2022 - Elsevier
With classical scaling of CMOS transistors according to Dennard's scaling rules running out
of steam, new possibilities to increase the functionality of an integrated circuit at a given …

Graphene spin valves for spin logic devices

P Ghising, C Biswas, YH Lee - Advanced Materials, 2023 - Wiley Online Library
An alternative to charge‐based electronics identifies the spin degree of freedom for
information communication and processing. The long spin‐diffusion length in graphene at …

Introduction to spin wave computing

A Mahmoud, F Ciubotaru, F Vanderveken… - Journal of Applied …, 2020 - pubs.aip.org
This paper provides a tutorial overview over recent vigorous efforts to develop computing
systems based on spin waves instead of charges and voltages. Spin-wave computing can …

Mana: A monolithic adiabatic integration architecture microprocessor using 1.4-zj/op unshunted superconductor josephson junction devices

CL Ayala, T Tanaka, R Saito, M Nozoe… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
We conducted the first successful demonstration of an adiabatic microprocessor based on
unshunted Josephson junction (JJ) devices manufactured using a Nb/AlO x/Nb …

[图书][B] Single Flux Quantum Integrated Circuit Design

G Krylov, EG Friedman - 2024 - Springer
Conventional semiconductor-based digital electronics, with complementary metal oxide
semiconductor (CMOS) technology as the primary example, has experienced meteoric …

20 Years of reconfigurable field-effect transistors: From concepts to future applications

T Mikolajick, G Galderisi, M Simon, S Rai, A Kumar… - Solid-State …, 2021 - Elsevier
The reconfigurable field-effect transistor (RFET), is an electronic device whose conduction
mechanism can be reversibly reconfigured between n-type and p-type operation modes. To …

LSOracle: A logic synthesis framework driven by artificial intelligence

WL Neto, M Austin, S Temple, L Amaru… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of
various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such …

On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis

H Riener, W Haaswijk, A Mishchenko… - … , Automation & Test …, 2019 - ieeexplore.ieee.org
The paper presents a generalization of DAG-aware AIG rewriting for k-feasible Boolean
networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG …

Efficient algorithms for in-memory fixed point multiplication using magic

A Haj-Ali, R Ben-Hur, N Wald… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
The growing disparity between processor and memory performance poses significant limits
on system performance and energy efficiency. To address this widely investigated problem …

Accelerated addition in resistive RAM array using parallel-friendly majority gates

J Reuben, S Pechmann - … on Very Large Scale Integration (VLSI …, 2021 - ieeexplore.ieee.org
To overcome the “von Neumann bottleneck,” methods to compute in memory are being
researched in many emerging memory technologies, including resistive RAMs (ReRAMs) …