Reconfigurable field effect transistors: A technology enablers perspective
With classical scaling of CMOS transistors according to Dennard's scaling rules running out
of steam, new possibilities to increase the functionality of an integrated circuit at a given …
of steam, new possibilities to increase the functionality of an integrated circuit at a given …
Graphene spin valves for spin logic devices
An alternative to charge‐based electronics identifies the spin degree of freedom for
information communication and processing. The long spin‐diffusion length in graphene at …
information communication and processing. The long spin‐diffusion length in graphene at …
Introduction to spin wave computing
This paper provides a tutorial overview over recent vigorous efforts to develop computing
systems based on spin waves instead of charges and voltages. Spin-wave computing can …
systems based on spin waves instead of charges and voltages. Spin-wave computing can …
Mana: A monolithic adiabatic integration architecture microprocessor using 1.4-zj/op unshunted superconductor josephson junction devices
CL Ayala, T Tanaka, R Saito, M Nozoe… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
We conducted the first successful demonstration of an adiabatic microprocessor based on
unshunted Josephson junction (JJ) devices manufactured using a Nb/AlO x/Nb …
unshunted Josephson junction (JJ) devices manufactured using a Nb/AlO x/Nb …
[图书][B] Single Flux Quantum Integrated Circuit Design
G Krylov, EG Friedman - 2024 - Springer
Conventional semiconductor-based digital electronics, with complementary metal oxide
semiconductor (CMOS) technology as the primary example, has experienced meteoric …
semiconductor (CMOS) technology as the primary example, has experienced meteoric …
20 Years of reconfigurable field-effect transistors: From concepts to future applications
The reconfigurable field-effect transistor (RFET), is an electronic device whose conduction
mechanism can be reversibly reconfigured between n-type and p-type operation modes. To …
mechanism can be reversibly reconfigured between n-type and p-type operation modes. To …
LSOracle: A logic synthesis framework driven by artificial intelligence
The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of
various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such …
various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such …
On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis
H Riener, W Haaswijk, A Mishchenko… - … , Automation & Test …, 2019 - ieeexplore.ieee.org
The paper presents a generalization of DAG-aware AIG rewriting for k-feasible Boolean
networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG …
networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG …
Efficient algorithms for in-memory fixed point multiplication using magic
The growing disparity between processor and memory performance poses significant limits
on system performance and energy efficiency. To address this widely investigated problem …
on system performance and energy efficiency. To address this widely investigated problem …
Accelerated addition in resistive RAM array using parallel-friendly majority gates
J Reuben, S Pechmann - … on Very Large Scale Integration (VLSI …, 2021 - ieeexplore.ieee.org
To overcome the “von Neumann bottleneck,” methods to compute in memory are being
researched in many emerging memory technologies, including resistive RAMs (ReRAMs) …
researched in many emerging memory technologies, including resistive RAMs (ReRAMs) …