The Intel® Core™ i7 processor code named Nehalem has a novel feature called Turbo
Boost which dynamically varies the frequencies of the processor's cores. The frequency of a …

A parallel implementation of the recently developed local pair natural orbital coupled
electron pair approximation (LPNO-CEPA/n, n= Version 1, 2, or 3) and the corresponding …

Translation Look aside Buffers (TLBs) are ubiquitously used in modern architectures to
cache virtual-to-physical mappings and, as they are looked up on every memory access, are …

We present a pipelined wavefront parallelization approach for stencil-based computations.
Within a fixed spatial domain successive wavefronts are executed by threads scheduled to a …

We explore the interplay between architectures and algorithm design in the context of
shared-memory platforms and a specific graph problem of central importance in scientific …

We present a new approach for parallel massive graph analysis of streaming, temporal data
with a dynamic and extensible representation. Handling the constant stream of new data …

This paper presents a survey of architectural features among four generations of Intel server
processors (Sandy Bridge, Ivy Bridge, Haswell, and Broadwell) with a focus on performance …

Process placement is a technique widely used on parallel machines with heterogeneous
interconnects to reduce the overall communication time. For instance, two processes which …

The Sparse Matrix-Vector Multiplication (SpMxV) kernel exhibits poor scaling on shared
memory systems, due to the streaming nature of its data access pattern. To decrease …

The use of graphics hardware for non-graphics applications has become popular among
many scientific programmers and researchers as we have observed a higher rate of …