Single-Event Upset Cross-Section Trends for D-FFs at the 5-and 7-nm Bulk FinFET Technology Nodes
At each advanced technology node, it is crucial to characterize and understand the
mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm …
mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm …
An SRAM SEU cross section curve physics model
D Kobayashi, K Hirose, K Sakamoto… - … on Nuclear Science, 2021 - ieeexplore.ieee.org
Static random access memories (SRAMs) are prone to a single-event upset (SEU), also
known as soft errors, due to transient noise caused by a single strike of radiation. Beam …
known as soft errors, due to transient noise caused by a single strike of radiation. Beam …
Scaling trends and the effect of process variations on the soft error rate of advanced FinFET SRAMs
B Narasimham, H Luk, C Paone… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
Scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in
the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7 …
the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7 …
Data-retention-voltage-based analysis of systematic variations in SRAM SEU hardness: A possible solution to synergistic effects of TID
D Kobayashi, K Hirose, K Sakamoto… - … on Nuclear Science, 2019 - ieeexplore.ieee.org
Single-event upset (SEU) hardness varies across dies, wafers, and lots—even just after
fabrication and further across time. Mechanisms of postfabrication variations include total …
fabrication and further across time. Mechanisms of postfabrication variations include total …
Single-event upsets in a 7-nm bulk FinFET technology with analysis of threshold voltage dependence
In this work, single-event upset (SEU) responses of D flip-flop (FF) designs with different
threshold-voltage options in a 7-nm bulk FinFET technology are examined. Experimental …
threshold-voltage options in a 7-nm bulk FinFET technology are examined. Experimental …
Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator
As Neural Processing Units (NPU) or accelerators are increasingly deployed in a variety of
applications including safety critical applications such as autonomous vehicle, and medical …
applications including safety critical applications such as autonomous vehicle, and medical …
A Method to Neutralize the Impact of DVS on the Reliability of COTS SRAMs with ECC by Using Periodic Scrubbing
Dynamic voltage scaling (DVS) can be used to reduce the power consumption of onboard
systems by dynamically lowering the bias voltage of volatile static random access memory …
systems by dynamically lowering the bias voltage of volatile static random access memory …
Threshold and Characteristic LETs in SRAM SEU Cross Section Curves
D Kobayashi, M Uematsu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Characterizing the sensitivity of a static random access memory (SRAM) to single-event
upset (SEU) is an essential task for assuring its soft-error reliability. However, this task often …
upset (SEU) is an essential task for assuring its soft-error reliability. However, this task often …
[PDF][PDF] 抗辐射电子学研究综述
曾超, 许献国, 钟乐 - Journal of terahertz science and electronic …, 2023 - researching.cn
抗辐射电子学是一门交叉性, 综合性的学科, 其研究的辐射效应规律, 损伤作用机制,
加固设计方法, 试验测试方法, 建模仿真方法等对极端恶劣环境中的电子系统的可靠工作至关 …
加固设计方法, 试验测试方法, 建模仿真方法等对极端恶劣环境中的电子系统的可靠工作至关 …
Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology
Abstract Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance
between the well boundary and N-channel metal–oxide semiconductor (NMOS) transistor or …
between the well boundary and N-channel metal–oxide semiconductor (NMOS) transistor or …